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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
debug
/
dmi.py
2022-02-20
Luke Kenneth Casso...
name core_stop and terminated_o synchronous to potentia...
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2022-01-19
Luke Kenneth Casso...
whoops forgot to enable fast-reg read in DMI
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2022-01-19
Luke Kenneth Casso...
ISI (0x400) trap is the only one that puts memory-based...
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2022-01-18
Luke Kenneth Casso...
add support for DMI debug read of FAST Regfile SPRs
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2021-12-19
Luke Kenneth Casso...
code-comments
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2021-12-19
Luke Kenneth Casso...
add DMI STOPADDR register and use it in HDLRunner to...
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2021-11-21
Luke Kenneth Casso...
complex. TestRunner now does not work properly unless...
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2021-03-07
Luke Kenneth Casso...
add SVSTATE read to DMI interface
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2020-09-22
Luke Kenneth Casso...
add jtag interface to issuer_verilog
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2020-09-21
Luke Kenneth Casso...
arg complete rewrite of JTAG2DMI, based it on staf...
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2020-08-29
Luke Kenneth Casso...
add hack to get at XER through DMI interface
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2020-08-25
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-25
Luke Kenneth Casso...
add CR read to DMI interface
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2020-08-25
Luke Kenneth Casso...
shorten using temp vars
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2020-08-25
Luke Kenneth Casso...
add CR DMI interface
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2020-08-03
Luke Kenneth Casso...
add quick demo/test of reading DMI reg 9
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2020-08-03
Luke Kenneth Casso...
use new soc.config.state CoreState class in DMI and...
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2020-08-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-08-03
Luke Kenneth Casso...
move debug to record
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2020-08-02
Luke Kenneth Casso...
convert microwatt core_debug.vhdl to nmigen
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