submodule update
[soc.git] / src / soc / debug / jtag.py
2021-04-08 Luke Kenneth Casso... argh, wb jtag stall probably is not working
2021-04-08 Luke Kenneth Casso... shrink JTAG master bus to 32-bit (match with litex)
2021-04-06 Luke Kenneth Casso... 8-bit granularity on JTAG wishbone
2021-02-21 Luke Kenneth Casso... add JTAG enable/disable of 4k SRAMs
2020-10-22 Luke Kenneth Casso... add means to JTAG interface to enable/disable "stuff...
2020-10-09 Luke Kenneth Casso... use libresoc version of c4m-jtag repo
2020-10-08 Luke Kenneth Casso... JTAG boundary scan test 1st attempt
2020-10-08 Luke Kenneth Casso... rework jtag test to use JTAG class not DMITAP
2020-10-04 Luke Kenneth Casso... significant reorg of the litex pinspecs to use pinmux...
2020-10-03 Luke Kenneth Casso... allow i2c to be routed via JTAG
2020-10-03 Luke Kenneth Casso... minor reorg on JTAG, allow alternative pinset dict...
2020-09-28 Luke Kenneth Casso... lots of sorting out iopads
2020-09-24 Luke Kenneth Casso... add comments
2020-09-24 Luke Kenneth Casso... c4m iopad integration working
2020-09-24 Luke Kenneth Casso... add jtag c4m pins which gives us a way to connect IO...
2020-09-22 Luke Kenneth Casso... add jtag interface to issuer_verilog
2020-09-22 Luke Kenneth Casso... add JTAG bus module