git.libre-soc.org Git - soc.git/history - src/soc/debug/test/test_jtag

2022-02-10	Andrey Miroshnikov	Added optional reverse arg to send TDI data MSB-first	blob \| commitdiff \| raw
2021-11-19	Tobias Platen	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2021-11-19	Luke Kenneth Casso...	for some reason DMI CTRL returns status of 0x6 not 0x0	blob \| commitdiff \| raw \| diff to current
2021-04-20	Luke Kenneth Casso...	use soc.bus.sram instead of nmigen_soc.wishbone.sram	blob \| commitdiff \| raw \| diff to current
2020-10-10	Luke Kenneth Casso...	add debug start/stop to firmware_upload script	blob \| commitdiff \| raw \| diff to current
2020-10-09	Luke Kenneth Casso...	use libresoc version of c4m-jtag repo	blob \| commitdiff \| raw \| diff to current
2020-09-22	Luke Kenneth Casso...	move dmi_sim to separate module	blob \| commitdiff \| raw \| diff to current
2020-09-22	Luke Kenneth Casso...	split out dmi2jtag into own unit test	blob \| commitdiff \| raw \| diff to current