Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / debug / test / test_jtag_tap_srv.py
2021-11-19 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-19 Luke Kenneth Casso... for some reason DMI CTRL returns status of 0x6 not 0x0
2021-11-19 Luke Kenneth Casso... missing argument, domain="sync" in JTAG instance
2021-04-20 Luke Kenneth Casso... use soc.bus.sram instead of nmigen_soc.wishbone.sram
2020-10-21 Luke Kenneth Casso... fix up asserts (check correct pads/cores)
2020-10-10 Luke Kenneth Casso... add debug start/stop to firmware_upload script
2020-10-09 Luke Kenneth Casso... missing yields in JTAG pads test to allow settling
2020-10-08 Luke Kenneth Casso... missing yields in JTAG pads test to allow settling
2020-10-08 Luke Kenneth Casso... JTAG boundary scan test 1st attempt
2020-10-08 Luke Kenneth Casso... rework jtag test to use JTAG class not DMITAP
2020-10-08 Luke Kenneth Casso... split out jtag util functions to separate module
2020-09-26 Luke Kenneth Casso... get openocd svf test running, replicating jtag test
2020-09-26 Luke Kenneth Casso... put test into "server" mode for connecting with openocd
2020-09-26 Luke Kenneth Casso... create client-server version of jtag debug unit test