bit of a big reorg of data structures
[soc.git] / src / soc / decoder / decode2execute1.py
2020-09-07 Luke Kenneth Casso... bit of a big reorg of data structures
2020-09-07 Luke Kenneth Casso... split out PowerDecode2 into PowerDecodeSubset
2020-09-07 Luke Kenneth Casso... allow Decode2ToExecute1Type to take an opkls argument
2020-08-29 Luke Kenneth Casso... slowly morphing towards using an XER bit-field selector...
2020-08-29 Luke Kenneth Casso... CR FXM becomes a full mask.
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB
2020-07-22 Luke Kenneth Casso... add TT.size and use it in PowerDecoder and trap input...
2020-07-21 Luke Kenneth Casso... add PC (CIA) to PowerDecode2 "state" for passing into...
2020-07-14 Luke Kenneth Casso... add MSR to PowerDecoder2
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-12 Luke Kenneth Casso... change CSV LD/ST update field to LDSTMode (support...
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth Casso... comment on spr2, not needed
2020-07-05 Luke Kenneth Casso... split out Decode2ToExecuteType fields involving registers
2020-07-05 Luke Kenneth Casso... sigh read and write xer detection, fix spr and trap...
2020-07-05 Luke Kenneth Casso... move valid signal out of Decode2ToExecute1Type and...
2020-07-05 Luke Kenneth Casso... remap SPR PowerISA numbers to internal SPR enum
2020-07-04 Luke Kenneth Casso... cater for illegal instruction (generates a trap)
2020-06-17 Luke Kenneth Casso... getting sim instruction decoder to reproduce asm instru...
2020-06-10 Luke Kenneth Casso... move Decode2ToExecute1Type to separate module