| 2021-03-17 |
Luke Kenneth Casso... | add twin-predicated extsw SVP64 ISACaller unit test |
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| 2021-03-17 |
Luke Kenneth Casso... | add SVP64 dststep incrementing in PowerDecoder2, Testis... |
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| 2021-03-17 |
Luke Kenneth Casso... | add CR-based predication to ISACaller |
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| 2021-03-17 |
Luke Kenneth Casso... | add SVP64 INT-style predication to ISACaller |
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| 2021-03-17 |
Luke Kenneth Casso... | add instr_fetch mode to ISACaller Mem and RADIXMMU |
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| 2021-03-13 |
Luke Kenneth Casso... | add setvl unit test assertions, add 2nd test |
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| 2021-03-13 |
Luke Kenneth Casso... | get first revision setvl operational in ISACaller |
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| 2021-03-13 |
Luke Kenneth Casso... | include SVSTATE in namespace, passing to ISACaller |
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| 2021-03-12 |
Luke Kenneth Casso... | **FOR NOW** LD/ST relies on detection of twin-predicati... |
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| 2021-03-11 |
Luke Kenneth Casso... | add in SVP64 LD/ST basic test for ISACaller |
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| 2021-03-11 |
Luke Kenneth Casso... | whoops sort out when svstate not active in ISACaller |
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| 2021-03-09 |
Luke Kenneth Casso... | debug radix mmu ISACaller |
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| 2021-03-09 |
Luke Kenneth Casso... | move Mem class out of ISACaller |
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| 2021-03-09 |
Luke Kenneth Casso... | move ISACaller RADIX MMU class to separate module |
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| 2021-03-09 |
Luke Kenneth Casso... | add pgtable and pte calculation to RADIX ISACaller |
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| 2021-03-08 |
Luke Kenneth Casso... | start adding _get_prtable_addr |
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| 2021-03-07 |
Cesar Strauss | Fix missing NIA update on ISACaller |
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| 2021-03-07 |
Tobias Platen | RADIX: read SPRs |
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| 2021-03-07 |
Tobias Platen | RADIX: implement memassign and call |
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| 2021-03-05 |
Luke Kenneth Casso... | add comments and more stub functions |
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| 2021-03-05 |
Luke Kenneth Casso... | add segment_check function, plus quick test. |
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| 2021-03-05 |
Luke Kenneth Casso... | add decode_prte function to RADIX |
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| 2021-03-05 |
Luke Kenneth Casso... | add trivial LD/ST redirectors into RADIX ISACaller |
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| 2021-03-04 |
Luke Kenneth Casso... | whitespace |
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| 2021-03-04 |
Tobias Platen | ISACaller: add option mmu |
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| 2021-03-04 |
Luke Kenneth Casso... | add comments from gem5-experimental mmu |
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| 2021-03-04 |
Luke Kenneth Casso... | add cached pgtbl0/3 |
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| 2021-03-04 |
Luke Kenneth Casso... | add two functions for checking permissions, to be based... |
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| 2021-03-03 |
Tobias Platen | add RADIX skeleton and unit test |
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| 2021-03-03 |
Luke Kenneth Casso... | add debug strings |
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| 2021-02-27 |
Luke Kenneth Casso... | use PowerDecoder2.no_out_vec instead of manual vector... |
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| 2021-02-21 |
Luke Kenneth Casso... | comments in SVP64RMFields |
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| 2021-02-21 |
Cesar Strauss | Use symbolic values as field sizes |
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| 2021-02-21 |
Cesar Strauss | Replace all hardcoded shifts into RM by usage of SVP64R... |
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| 2021-02-20 |
Luke Kenneth Casso... | add in Vectorised CRs when Rc=1 into ISACaller |
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| 2021-02-20 |
Luke Kenneth Casso... | add some debug checking to get_pdecode_cr_out |
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| 2021-02-20 |
Luke Kenneth Casso... | add more debug output to get_pdecode_cr_out |
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| 2021-02-20 |
Cesar Strauss | Assemble the SV64 prefix from its subfields using SVP64... |
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| 2021-02-20 |
Luke Kenneth Casso... | start on CRs in SVP64 mode |
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| 2021-02-17 |
Luke Kenneth Casso... | fix reg read/write in ISACaller, PowerDecoder2 handles... |
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| 2021-02-16 |
Cesar Strauss | Fix MSB0 issues for SVP64 |
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| 2021-02-16 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2021-02-16 |
Luke Kenneth Casso... | ordering wrong on svstate in ISACaller |
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| 2021-02-12 |
Luke Kenneth Casso... | add skip of instruction if SVSTATE.VL=0 in ISACaller |
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| 2021-02-12 |
Luke Kenneth Casso... | add srcstep and correct PC-advancing during Sub-PC... |
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| 2021-02-12 |
Luke Kenneth Casso... | comments |
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| 2021-02-12 |
Luke Kenneth Casso... | add in SVSTATE.srcstep update, loop from 0 to VL-1 |
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| 2021-02-12 |
Luke Kenneth Casso... | allow PC to update by 8 in SVP64 mode |
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| 2021-02-12 |
Luke Kenneth Casso... | fix setting of SVSTATE.VL and MVL |
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| 2021-02-12 |
Luke Kenneth Casso... | add in SVSTATE to ISACaller, not used, just passed in |
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| 2021-02-10 |
Luke Kenneth Casso... | add svp64 reg decode detection to ISACaller output |
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| 2021-02-10 |
Luke Kenneth Casso... | starting to add SVP64 register EXTRA-read and isvec... |
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| 2021-02-10 |
Luke Kenneth Casso... | comment update |
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| 2021-02-01 |
Luke Kenneth Casso... | ISACaller, in svp64 mode, read the next 32 bits when... |
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| 2021-02-01 |
Luke Kenneth Casso... | sort out SelectableInt bit-ordering for identifying... |
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| 2021-01-31 |
Luke Kenneth Casso... | test SVP64 major opcode, start checking if it is EXT001... |
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| 2021-01-31 |
Luke Kenneth Casso... | adjusting ISACaller unit test to use ISACaller.setup_one() |
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| 2021-01-31 |
Tobias Platen | fix two syntax errors in src/soc/decoder/isa/caller.py |
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| 2021-01-31 |
Luke Kenneth Casso... | SVP64 Remap Fields structures for ISACaller |
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| 2021-01-31 |
Luke Kenneth Casso... | remove sv_rm from PowerDecoder register decoders |
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| 2021-01-31 |
Luke Kenneth Casso... | add SVSTATE SPR sub-field accessor class to ISACaller |
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| 2020-10-09 |
Luke Kenneth Casso... | drop in "undefined" function into ISAcaller namespace |
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| 2020-10-05 |
Jacob Lifshay | simplify create_args |
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| 2020-10-05 |
Jacob Lifshay | Sort returned variables to make sure `overflow` is... |
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| 2020-10-05 |
Jacob Lifshay | format caller.py |
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| 2020-09-07 |
Luke Kenneth Casso... | whoops spelling mistake outOut_carry not outPut_carry |
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| 2020-09-07 |
Luke Kenneth Casso... | convert mul test to use Power Decode subset |
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| 2020-09-07 |
Luke Kenneth Casso... | convert CR to PowerDecodeSubset format |
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| 2020-09-07 |
Luke Kenneth Casso... | bit of a big reorg of data structures |
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| 2020-09-02 |
Luke Kenneth Casso... | add bc ctr regression test when CTR=0 and CTR=1 |
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| 2020-09-02 |
Luke Kenneth Casso... | series of extensive modifications to fix long-standing... |
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| 2020-08-27 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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| 2020-08-27 |
Luke Kenneth Casso... | really bad hack to fix simulator bug in carry handling |
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| 2020-08-24 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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| 2020-08-22 |
Luke Kenneth Casso... | rename invert_a to invert_in because logical inverts RB |
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| 2020-08-17 |
Luke Kenneth Casso... | turn SelectableInt less/greater into signed versions. |
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| 2020-08-14 |
Luke Kenneth Casso... | bad hack to get HSRR0/1 to be "same" as SRR0/1 |
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| 2020-08-04 |
Luke Kenneth Casso... | tracked down byte-reversal in LDST ISACaller and LDSTCo... |
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| 2020-08-04 |
Luke Kenneth Casso... | whitespace after autopep8 messed up |
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| 2020-08-04 |
Luke Kenneth Casso... | msr and pc moved to "state" in PowerDecode2 |
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| 2020-08-01 |
Luke Kenneth Casso... | add quick test of litex bios IMM64 macro |
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| 2020-07-25 |
Luke Kenneth Casso... | hilarious. only just caught a bug where overflow was... |
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| 2020-07-24 |
Luke Kenneth Casso... | annoying, yet more typos |
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| 2020-07-24 |
Luke Kenneth Casso... | annoying, typo |
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| 2020-07-24 |
Luke Kenneth Casso... | better debug assert log message |
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| 2020-07-24 |
Luke Kenneth Casso... | restore modification to caller.py from reversion of... |
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| 2020-07-24 |
Luke Kenneth Casso... | Revert "working on div's test_pipe_caller" |
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| 2020-07-24 |
Jacob Lifshay | working on div's test_pipe_caller |
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| 2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
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| 2020-07-22 |
Jacob Lifshay | format code |
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| 2020-07-22 |
Luke Kenneth Casso... | set additional MSR bits according to v3.0B spec when... |
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| 2020-07-22 |
Luke Kenneth Casso... | use (new) MSRb and PIb which has auto-bigendian numbers |
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| 2020-07-21 |
Luke Kenneth Casso... | convert branch pipeline to use msr/cia as immediates |
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| 2020-07-21 |
Luke Kenneth Casso... | set ISACaller.msr rather than namespace[MSR] |
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| 2020-07-21 |
Luke Kenneth Casso... | add msr exception bits setting function in hardware |
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| 2020-07-16 |
Luke Kenneth Casso... | get trap compunit test working, adding bigendian and msr |
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| 2020-07-15 |
Luke Kenneth Casso... | whoops forgot to update PC after trap in ISACaller |
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| 2020-07-14 |
Luke Kenneth Casso... | attempting to access self.msr directly |
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| 2020-07-14 |
Luke Kenneth Casso... | add priv instruction checking to ISACaller simulator |
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| 2020-07-12 |
Luke Kenneth Casso... | rename InternalOp to MicrOp |
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