2020-07-10 |
Luke Kenneth Casso... | add a DIVS function as separate and discrete from floor_div |
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2020-07-10 |
Luke Kenneth Casso... | check for div_overflow equal to None rather than == 1 |
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2020-07-09 |
Luke Kenneth Casso... | debug information related to 32/64 bit mode |
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2020-07-09 |
Luke Kenneth Casso... | identifying locations where big/little endian is in... |
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2020-07-08 |
Luke Kenneth Casso... | stashing current state of investigation whilst looking... |
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2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-07-07 |
Luke Kenneth Casso... | ordering of tests for OP_ATTN needed shuffling. seems... |
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2020-07-07 |
Luke Kenneth Casso... | add halted condition in ISACaller, when attn instructio... |
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2020-07-05 |
Luke Kenneth Casso... | add mtmsr tests (fail) |
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2020-07-05 |
Luke Kenneth Casso... | add an illegal instruction trap test |
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2020-07-05 |
Luke Kenneth Casso... | big reorg on PowerDecoder2, actually Decode2Execute1Type |
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2020-07-05 |
Luke Kenneth Casso... | missing initialisation of disasm_start |
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2020-07-05 |
Luke Kenneth Casso... | fix qemu trap test |
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2020-07-04 |
Luke Kenneth Casso... | use new consts module |
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2020-07-04 |
Luke Kenneth Casso... | sorting out trap fastregs |
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2020-07-04 |
Luke Kenneth Casso... | resolve spr names in ISACaller |
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2020-07-04 |
Luke Kenneth Casso... | debugging decoding of SPRs (fast) |
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2020-07-01 |
Luke Kenneth Casso... | whoops missed some cases in unit test changing ALUHelpers |
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2020-07-01 |
Luke Kenneth Casso... | print out msr for debug |
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2020-07-01 |
Luke Kenneth Casso... | attempting to add SPRs to rfid test |
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2020-06-29 |
Luke Kenneth Casso... | update OV and OV32 ISACaller flags if overflow occurs |
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2020-06-29 |
Luke Kenneth Casso... | attempting to add overflow setting in ISACaller |
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2020-06-20 |
colepoirier | Add code, commented-out, for TRAP so as to not break... |
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2020-06-19 |
Luke Kenneth Casso... | add trunc_div and trunch_rem to decoder helpers |
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2020-06-19 |
Luke Kenneth Casso... | bit of a mess. getting carry recognised and output... |
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2020-06-18 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-18 |
Luke Kenneth Casso... | investigating mtocrf/mtcrf issue |
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2020-06-17 |
Luke Kenneth Casso... | add bug reference to mtocrf/mtcrf name decoding |
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2020-06-17 |
Luke Kenneth Casso... | decoding assembly instruction name, move to separate... |
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2020-06-17 |
Luke Kenneth Casso... | getting sim instruction decoder to reproduce asm instru... |
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2020-06-17 |
Luke Kenneth Casso... | update test_sim.py to do a simple execution loop: decod... |
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2020-06-17 |
Luke Kenneth Casso... | get fu compunit test to use ISACaller instruction-memory |
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2020-06-17 |
Luke Kenneth Casso... | split execute and setup of ISACaller instruction execution |
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2020-06-17 |
Luke Kenneth Casso... | comment ISACaller setup |
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2020-06-17 |
Luke Kenneth Casso... | start to add in independent execution into ISACaller |
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2020-06-17 |
Luke Kenneth Casso... | add a fake program counter to ISACaller |
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2020-06-17 |
Luke Kenneth Casso... | add "respect_pc" boolean to ISACaller |
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2020-06-17 |
Luke Kenneth Casso... | add optional instruction memory |
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2020-06-17 |
Luke Kenneth Casso... | got test_issuer FSM operating. bit of a hack |
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2020-06-14 |
Luke Kenneth Casso... | reasonably certain that the careful and slow use of... |
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2020-06-12 |
Luke Kenneth Casso... | note possible BE/LE mode needed for memory reads/writes |
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2020-06-12 |
Luke Kenneth Casso... | tracking down what looks like an error in the Simulator... |
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2020-06-08 |
Luke Kenneth Casso... | add comment docstring about POWER9 simulator |
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2020-06-08 |
Luke Kenneth Casso... | whoops, overflow-decode (handle_overflow) needed to... |
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2020-06-08 |
Luke Kenneth Casso... | check that carry has already been done or not by the... |
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2020-06-08 |
Luke Kenneth Casso... | copy 64-bit OV, try creating 32-bit OV32 in |
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2020-06-07 |
Luke Kenneth Casso... | update comments |
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2020-06-07 |
Luke Kenneth Casso... | ha! set XER CA/CA32 in simulator from output.value... |
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2020-06-07 |
Luke Kenneth Casso... | optionally writing out CA/CA32 to XER |
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2020-06-07 |
Luke Kenneth Casso... | add handling of CA/CA32 in simulator, generated from... |
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2020-06-07 |
Luke Kenneth Casso... | docstring on caller.py inject() decorator |
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2020-06-07 |
Luke Kenneth Casso... | add TRAP function, stub |
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2020-06-07 |
Luke Kenneth Casso... | add MSR to simulator context |
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2020-06-06 |
Luke Kenneth Casso... | experimenting with setting up and testing memory |
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2020-06-06 |
Luke Kenneth Casso... | shift-mask in Simulator Mem class not quite right |
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2020-06-06 |
Luke Kenneth Casso... | allow Mem in Simulator to be initialised |
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2020-05-21 |
Michael Nolan | Fix broken unit tests in test_caller |
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2020-05-21 |
Michael Nolan | Fix broken test_adde/add overflow handling to caller.py |
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2020-05-19 |
Michael Nolan | Fix weird edge cases with carry |
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2020-05-19 |
Michael Nolan | Add ca32 to caller.py |
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2020-05-19 |
Michael Nolan | Handle carry in caller.py |
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2020-05-16 |
Michael Nolan | Get working mcrf in caller.py |
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2020-05-15 |
Michael Nolan | Add ability to specify initial CR state |
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2020-05-15 |
Michael Nolan | Implement relative branches, add explicit NIA input... |
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2020-05-15 |
Michael Nolan | Add test for popcnt to test_caller.py |
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2020-05-14 |
Luke Kenneth Casso... | simplify popcount |
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2020-05-13 |
Michael Nolan | Update TODO |
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2020-05-11 |
Michael Nolan | Add ability to specify initial state for SPRs |
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2020-05-07 |
Michael Nolan | Get test_cmp working |
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2020-05-07 |
Michael Nolan | Add handling of add with comparison |
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2020-05-06 |
Michael Nolan | Look up spr length from spr table |
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2020-05-06 |
Michael Nolan | Implement bctr and mtspr |
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2020-05-06 |
Michael Nolan | Properly implement LR and CTR |
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2020-05-06 |
Michael Nolan | Sorta kinda working bl and blr - need to properly imple... |
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2020-05-05 |
Michael Nolan | Add rudimentary branch capability |
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2020-04-17 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-04-07 |
Luke Kenneth Casso... | try making CR bitrange 32..63 not 0..31 |
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2020-04-07 |
Luke Kenneth Casso... | note that CR must be offset by 32 |
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2020-04-07 |
Luke Kenneth Casso... | add "undefined" to namespace |
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2020-04-07 |
Luke Kenneth Casso... | CR test "working" (for a given value of "success") |
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2020-04-07 |
Luke Kenneth Casso... | add in special regs to be passed out of function (as... |
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2020-04-07 |
Luke Kenneth Casso... | attempting to add mtcrf test, requires bringing CR... |
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2020-04-07 |
Luke Kenneth Casso... | op_fields is passed over (and excludes register names) |
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2020-04-07 |
Luke Kenneth Casso... | add CR and add field-selectable versions of CR0-7 |
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2020-04-07 |
Luke Kenneth Casso... | whew finally located opcodes for managing CRs |
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2020-04-06 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-04-06 |
Luke Kenneth Casso... | add extra info on SPRs |
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2020-04-06 |
Luke Kenneth Casso... | add list of SPRs needed |
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2020-04-06 |
Jacob Lifshay | Merge branch 'fix-tests' |
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2020-04-06 |
Michael Nolan | Convert instruction info from tuple to namedtuple |
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2020-04-06 |
Michael Nolan | Begin adding PC to caller.py |
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2020-04-06 |
Michael Nolan | Auto insert instruction fields into the namespace |
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2020-04-05 |
Luke Kenneth Casso... | put regs through to ISACaller |
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2020-04-05 |
Luke Kenneth Casso... | add comment about form / op_fields |
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2020-04-05 |
Luke Kenneth Casso... | unpack tuple with new op_fields |
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2020-04-05 |
Michael Nolan | Handle new changes in pseudocode parser |
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2020-04-05 |
Michael Nolan | Handle opcodes returning EXTS() results |
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2020-04-05 |
Michael Nolan | Add in _reg and immediate support |
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2020-04-05 |
Michael Nolan | Fix issue with memory load/store byte order |
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2020-04-05 |
Luke Kenneth Casso... | Revert "Implement bug 278, comment 1 - better version... |
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