replace PartitionedSignal with SimdSignal
[soc.git] / src / soc / decoder / isa / caller.py
2021-04-23 Luke Kenneth Casso... more openpower import conversion
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-04-15 Luke Kenneth Casso... add icachemmu option to ISACaller
2021-04-13 Tobias Platenfix AttributeError in radixmmu testcase
2021-04-03 Cesar StraussFix typo
2021-04-02 Cesar StraussEnd VL loop as soon as either src/dst step reaches VL
2021-04-02 Cesar StraussFix typo
2021-03-20 Luke Kenneth Casso... sort out predicate zeroing in ISACaller
2021-03-20 Luke Kenneth Casso... attempting to add src/dest-zeroing to ISACaller
2021-03-18 Luke Kenneth Casso... comments / code-shuffle
2021-03-17 Luke Kenneth Casso... add twin-predicated extsw SVP64 ISACaller unit test
2021-03-17 Luke Kenneth Casso... add SVP64 dststep incrementing in PowerDecoder2, Testis...
2021-03-17 Luke Kenneth Casso... add CR-based predication to ISACaller
2021-03-17 Luke Kenneth Casso... add SVP64 INT-style predication to ISACaller
2021-03-17 Luke Kenneth Casso... add instr_fetch mode to ISACaller Mem and RADIXMMU
2021-03-13 Luke Kenneth Casso... add setvl unit test assertions, add 2nd test
2021-03-13 Luke Kenneth Casso... get first revision setvl operational in ISACaller
2021-03-13 Luke Kenneth Casso... include SVSTATE in namespace, passing to ISACaller
2021-03-12 Luke Kenneth Casso... **FOR NOW** LD/ST relies on detection of twin-predicati...
2021-03-11 Luke Kenneth Casso... add in SVP64 LD/ST basic test for ISACaller
2021-03-11 Luke Kenneth Casso... whoops sort out when svstate not active in ISACaller
2021-03-09 Luke Kenneth Casso... debug radix mmu ISACaller
2021-03-09 Luke Kenneth Casso... move Mem class out of ISACaller
2021-03-09 Luke Kenneth Casso... move ISACaller RADIX MMU class to separate module
2021-03-09 Luke Kenneth Casso... add pgtable and pte calculation to RADIX ISACaller
2021-03-08 Luke Kenneth Casso... start adding _get_prtable_addr
2021-03-07 Cesar StraussFix missing NIA update on ISACaller
2021-03-07 Tobias PlatenRADIX: read SPRs
2021-03-07 Tobias PlatenRADIX: implement memassign and call
2021-03-05 Luke Kenneth Casso... add comments and more stub functions
2021-03-05 Luke Kenneth Casso... add segment_check function, plus quick test.
2021-03-05 Luke Kenneth Casso... add decode_prte function to RADIX
2021-03-05 Luke Kenneth Casso... add trivial LD/ST redirectors into RADIX ISACaller
2021-03-04 Luke Kenneth Casso... whitespace
2021-03-04 Tobias PlatenISACaller: add option mmu
2021-03-04 Luke Kenneth Casso... add comments from gem5-experimental mmu
2021-03-04 Luke Kenneth Casso... add cached pgtbl0/3
2021-03-04 Luke Kenneth Casso... add two functions for checking permissions, to be based...
2021-03-03 Tobias Platenadd RADIX skeleton and unit test
2021-03-03 Luke Kenneth Casso... add debug strings
2021-02-27 Luke Kenneth Casso... use PowerDecoder2.no_out_vec instead of manual vector...
2021-02-21 Luke Kenneth Casso... comments in SVP64RMFields
2021-02-21 Cesar StraussUse symbolic values as field sizes
2021-02-21 Cesar StraussReplace all hardcoded shifts into RM by usage of SVP64R...
2021-02-20 Luke Kenneth Casso... add in Vectorised CRs when Rc=1 into ISACaller
2021-02-20 Luke Kenneth Casso... add some debug checking to get_pdecode_cr_out
2021-02-20 Luke Kenneth Casso... add more debug output to get_pdecode_cr_out
2021-02-20 Cesar StraussAssemble the SV64 prefix from its subfields using SVP64...
2021-02-20 Luke Kenneth Casso... start on CRs in SVP64 mode
2021-02-17 Luke Kenneth Casso... fix reg read/write in ISACaller, PowerDecoder2 handles...
2021-02-16 Cesar StraussFix MSB0 issues for SVP64
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-16 Luke Kenneth Casso... ordering wrong on svstate in ISACaller
2021-02-12 Luke Kenneth Casso... add skip of instruction if SVSTATE.VL=0 in ISACaller
2021-02-12 Luke Kenneth Casso... add srcstep and correct PC-advancing during Sub-PC...
2021-02-12 Luke Kenneth Casso... comments
2021-02-12 Luke Kenneth Casso... add in SVSTATE.srcstep update, loop from 0 to VL-1
2021-02-12 Luke Kenneth Casso... allow PC to update by 8 in SVP64 mode
2021-02-12 Luke Kenneth Casso... fix setting of SVSTATE.VL and MVL
2021-02-12 Luke Kenneth Casso... add in SVSTATE to ISACaller, not used, just passed in
2021-02-10 Luke Kenneth Casso... add svp64 reg decode detection to ISACaller output
2021-02-10 Luke Kenneth Casso... starting to add SVP64 register EXTRA-read and isvec...
2021-02-10 Luke Kenneth Casso... comment update
2021-02-01 Luke Kenneth Casso... ISACaller, in svp64 mode, read the next 32 bits when...
2021-02-01 Luke Kenneth Casso... sort out SelectableInt bit-ordering for identifying...
2021-01-31 Luke Kenneth Casso... test SVP64 major opcode, start checking if it is EXT001...
2021-01-31 Luke Kenneth Casso... adjusting ISACaller unit test to use ISACaller.setup_one()
2021-01-31 Tobias Platenfix two syntax errors in src/soc/decoder/isa/caller.py
2021-01-31 Luke Kenneth Casso... SVP64 Remap Fields structures for ISACaller
2021-01-31 Luke Kenneth Casso... remove sv_rm from PowerDecoder register decoders
2021-01-31 Luke Kenneth Casso... add SVSTATE SPR sub-field accessor class to ISACaller
2020-10-09 Luke Kenneth Casso... drop in "undefined" function into ISAcaller namespace
2020-10-05 Jacob Lifshaysimplify create_args
2020-10-05 Jacob LifshaySort returned variables to make sure `overflow` is...
2020-10-05 Jacob Lifshayformat caller.py
2020-09-07 Luke Kenneth Casso... whoops spelling mistake outOut_carry not outPut_carry
2020-09-07 Luke Kenneth Casso... convert mul test to use Power Decode subset
2020-09-07 Luke Kenneth Casso... convert CR to PowerDecodeSubset format
2020-09-07 Luke Kenneth Casso... bit of a big reorg of data structures
2020-09-02 Luke Kenneth Casso... add bc ctr regression test when CTR=0 and CTR=1
2020-09-02 Luke Kenneth Casso... series of extensive modifications to fix long-standing...
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... really bad hack to fix simulator bug in carry handling
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB
2020-08-17 Luke Kenneth Casso... turn SelectableInt less/greater into signed versions.
2020-08-14 Luke Kenneth Casso... bad hack to get HSRR0/1 to be "same" as SRR0/1
2020-08-04 Luke Kenneth Casso... tracked down byte-reversal in LDST ISACaller and LDSTCo...
2020-08-04 Luke Kenneth Casso... whitespace after autopep8 messed up
2020-08-04 Luke Kenneth Casso... msr and pc moved to "state" in PowerDecode2
2020-08-01 Luke Kenneth Casso... add quick test of litex bios IMM64 macro
2020-07-25 Luke Kenneth Casso... hilarious. only just caught a bug where overflow was...
2020-07-24 Luke Kenneth Casso... annoying, yet more typos
2020-07-24 Luke Kenneth Casso... annoying, typo
2020-07-24 Luke Kenneth Casso... better debug assert log message
2020-07-24 Luke Kenneth Casso... restore modification to caller.py from reversion of...
2020-07-24 Luke Kenneth Casso... Revert "working on div's test_pipe_caller"
2020-07-24 Jacob Lifshayworking on div's test_pipe_caller
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
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