annoying, yet more typos
[soc.git] / src / soc / decoder / isa / caller.py
2020-07-24 Luke Kenneth Casso... annoying, yet more typos
2020-07-24 Luke Kenneth Casso... annoying, typo
2020-07-24 Luke Kenneth Casso... better debug assert log message
2020-07-24 Luke Kenneth Casso... restore modification to caller.py from reversion of...
2020-07-24 Luke Kenneth Casso... Revert "working on div's test_pipe_caller"
2020-07-24 Jacob Lifshayworking on div's test_pipe_caller
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-22 Luke Kenneth Casso... set additional MSR bits according to v3.0B spec when...
2020-07-22 Luke Kenneth Casso... use (new) MSRb and PIb which has auto-bigendian numbers
2020-07-21 Luke Kenneth Casso... convert branch pipeline to use msr/cia as immediates
2020-07-21 Luke Kenneth Casso... set ISACaller.msr rather than namespace[MSR]
2020-07-21 Luke Kenneth Casso... add msr exception bits setting function in hardware
2020-07-16 Luke Kenneth Casso... get trap compunit test working, adding bigendian and msr
2020-07-15 Luke Kenneth Casso... whoops forgot to update PC after trap in ISACaller
2020-07-14 Luke Kenneth Casso... attempting to access self.msr directly
2020-07-14 Luke Kenneth Casso... add priv instruction checking to ISACaller simulator
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-11 Luke Kenneth Casso... special test for mul hw to cope with ignoring OE flag
2020-07-10 Luke Kenneth Casso... add a DIVS function as separate and discrete from floor_div
2020-07-10 Luke Kenneth Casso... check for div_overflow equal to None rather than == 1
2020-07-09 Luke Kenneth Casso... debug information related to 32/64 bit mode
2020-07-09 Luke Kenneth Casso... identifying locations where big/little endian is in...
2020-07-08 Luke Kenneth Casso... stashing current state of investigation whilst looking...
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... ordering of tests for OP_ATTN needed shuffling. seems...
2020-07-07 Luke Kenneth Casso... add halted condition in ISACaller, when attn instructio...
2020-07-05 Luke Kenneth Casso... add mtmsr tests (fail)
2020-07-05 Luke Kenneth Casso... add an illegal instruction trap test
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth Casso... missing initialisation of disasm_start
2020-07-05 Luke Kenneth Casso... fix qemu trap test
2020-07-04 Luke Kenneth Casso... use new consts module
2020-07-04 Luke Kenneth Casso... sorting out trap fastregs
2020-07-04 Luke Kenneth Casso... resolve spr names in ISACaller
2020-07-04 Luke Kenneth Casso... debugging decoding of SPRs (fast)
2020-07-01 Luke Kenneth Casso... whoops missed some cases in unit test changing ALUHelpers
2020-07-01 Luke Kenneth Casso... print out msr for debug
2020-07-01 Luke Kenneth Casso... attempting to add SPRs to rfid test
2020-06-29 Luke Kenneth Casso... update OV and OV32 ISACaller flags if overflow occurs
2020-06-29 Luke Kenneth Casso... attempting to add overflow setting in ISACaller
2020-06-20 colepoirierAdd code, commented-out, for TRAP so as to not break...
2020-06-19 Luke Kenneth Casso... add trunc_div and trunch_rem to decoder helpers
2020-06-19 Luke Kenneth Casso... bit of a mess. getting carry recognised and output...
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Luke Kenneth Casso... investigating mtocrf/mtcrf issue
2020-06-17 Luke Kenneth Casso... add bug reference to mtocrf/mtcrf name decoding
2020-06-17 Luke Kenneth Casso... decoding assembly instruction name, move to separate...
2020-06-17 Luke Kenneth Casso... getting sim instruction decoder to reproduce asm instru...
2020-06-17 Luke Kenneth Casso... update test_sim.py to do a simple execution loop: decod...
2020-06-17 Luke Kenneth Casso... get fu compunit test to use ISACaller instruction-memory
2020-06-17 Luke Kenneth Casso... split execute and setup of ISACaller instruction execution
2020-06-17 Luke Kenneth Casso... comment ISACaller setup
2020-06-17 Luke Kenneth Casso... start to add in independent execution into ISACaller
2020-06-17 Luke Kenneth Casso... add a fake program counter to ISACaller
2020-06-17 Luke Kenneth Casso... add "respect_pc" boolean to ISACaller
2020-06-17 Luke Kenneth Casso... add optional instruction memory
2020-06-17 Luke Kenneth Casso... got test_issuer FSM operating. bit of a hack
2020-06-14 Luke Kenneth Casso... reasonably certain that the careful and slow use of...
2020-06-12 Luke Kenneth Casso... note possible BE/LE mode needed for memory reads/writes
2020-06-12 Luke Kenneth Casso... tracking down what looks like an error in the Simulator...
2020-06-08 Luke Kenneth Casso... add comment docstring about POWER9 simulator
2020-06-08 Luke Kenneth Casso... whoops, overflow-decode (handle_overflow) needed to...
2020-06-08 Luke Kenneth Casso... check that carry has already been done or not by the...
2020-06-08 Luke Kenneth Casso... copy 64-bit OV, try creating 32-bit OV32 in
2020-06-07 Luke Kenneth Casso... update comments
2020-06-07 Luke Kenneth Casso... ha! set XER CA/CA32 in simulator from output.value...
2020-06-07 Luke Kenneth Casso... optionally writing out CA/CA32 to XER
2020-06-07 Luke Kenneth Casso... add handling of CA/CA32 in simulator, generated from...
2020-06-07 Luke Kenneth Casso... docstring on caller.py inject() decorator
2020-06-07 Luke Kenneth Casso... add TRAP function, stub
2020-06-07 Luke Kenneth Casso... add MSR to simulator context
2020-06-06 Luke Kenneth Casso... experimenting with setting up and testing memory
2020-06-06 Luke Kenneth Casso... shift-mask in Simulator Mem class not quite right
2020-06-06 Luke Kenneth Casso... allow Mem in Simulator to be initialised
2020-05-21 Michael NolanFix broken unit tests in test_caller
2020-05-21 Michael NolanFix broken test_adde/add overflow handling to caller.py
2020-05-19 Michael NolanFix weird edge cases with carry
2020-05-19 Michael NolanAdd ca32 to caller.py
2020-05-19 Michael NolanHandle carry in caller.py
2020-05-16 Michael NolanGet working mcrf in caller.py
2020-05-15 Michael NolanAdd ability to specify initial CR state
2020-05-15 Michael NolanImplement relative branches, add explicit NIA input...
2020-05-15 Michael NolanAdd test for popcnt to test_caller.py
2020-05-14 Luke Kenneth Casso... simplify popcount
2020-05-13 Michael NolanUpdate TODO
2020-05-11 Michael NolanAdd ability to specify initial state for SPRs
2020-05-07 Michael NolanGet test_cmp working
2020-05-07 Michael NolanAdd handling of add with comparison
2020-05-06 Michael NolanLook up spr length from spr table
2020-05-06 Michael NolanImplement bctr and mtspr
2020-05-06 Michael NolanProperly implement LR and CTR
2020-05-06 Michael NolanSorta kinda working bl and blr - need to properly imple...
2020-05-05 Michael NolanAdd rudimentary branch capability
2020-04-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-04-07 Luke Kenneth Casso... try making CR bitrange 32..63 not 0..31
2020-04-07 Luke Kenneth Casso... note that CR must be offset by 32
2020-04-07 Luke Kenneth Casso... add "undefined" to namespace
2020-04-07 Luke Kenneth Casso... CR test "working" (for a given value of "success")
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