getting sim instruction decoder to reproduce asm instruction disassembly
[soc.git] / src / soc / decoder / power_decoder.py
2020-06-17 Luke Kenneth Casso... getting sim instruction decoder to reproduce asm instru...
2020-06-17 Luke Kenneth Casso... add comment/assembly decode in power enums
2020-05-21 Luke Kenneth Casso... add CR out decoder debug
2020-05-21 Michael NolanConvert CR out to enum in power_decoder
2020-05-21 Michael NolanConvert CR In field to enum instead of single bit
2020-05-13 Michael NolanFix too wide bitfield being selected for opcode 30
2020-05-09 Luke Kenneth Casso... document PowerOp
2020-05-05 Yehowshua ImmanuelMerge branch 'master' of git.libre-riscv.org:soc
2020-05-05 Yehowshua ImmanuelGit rid of named tuple imported twice
2020-05-03 Luke Kenneth Casso... add comments to power decoder
2020-03-31 Luke Kenneth Casso... split out sig set from sig setup
2020-03-30 Michael NolanMinor cleanup
2020-03-30 Luke Kenneth Casso... add signals for all fields, accessible by named tuples...
2020-03-30 Michael NolanWIP: Replace fields in power_decoder with signals of...
2020-03-21 Luke Kenneth Casso... mention instruction fetch mapping section
2020-03-21 Luke Kenneth Casso... add big/little byte-reversing
2020-03-18 Luke Kenneth Casso... add comments
2020-03-09 Michael NolanMigrate imports to use absolute imports
2020-03-09 Luke Kenneth Casso... move all source directories to soc so that "import...