attempting to add SPRs to rfid test
[soc.git] / src / soc / decoder / power_regspec_map.py
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Luke Kenneth Casso... code-morph regspecmap functions, split into separate...
2020-06-05 Luke Kenneth Casso... whoops returning cr2 for cr3 regspec map
2020-06-05 Luke Kenneth Casso... fix syntax errors and use correct FastRegs (SRR0/1...
2020-06-04 Luke Kenneth Casso... sigh. because POWER. CR index inversion
2020-06-03 Luke Kenneth Casso... correct comments on regspec decode map
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... worked out how to dynamically enable carry-in to ALU...
2020-06-03 Luke Kenneth Casso... correct overflow-enable flags for rdmask specs in ALU
2020-06-03 Luke Kenneth Casso... attempt to make carry-in and overflow-enable optional...
2020-06-03 Luke Kenneth Casso... move over to using power_regspec_map.py from PowerDecod...
2020-06-03 Luke Kenneth Casso... mention TODO on SPR regfile
2020-06-02 Luke Kenneth Casso... move regspec function to separate module