radix: reading first page table entry
[soc.git] / src / soc / decoder /
2021-03-10 Tobias Platenradix: reading first page table entry
2021-03-10 Luke Kenneth Casso... add walk_tree arguments it needs
2021-03-09 Luke Kenneth Casso... fix address must convert to SelectableInt
2021-03-09 Luke Kenneth Casso... call decode_ptre on address to obtain shift, mbits...
2021-03-09 Tobias Platenwhitespace
2021-03-09 Tobias PlatenRADIX: call self._walk_tree in ld and st
2021-03-09 Luke Kenneth Casso... debug radix mmu ISACaller
2021-03-09 Tobias Platencomment out broken spr code
2021-03-09 Tobias Platen_walk_tree: access sprs
2021-03-09 Luke Kenneth Casso... create first check_perms RADIX ISACaller function
2021-03-09 Luke Kenneth Casso... move Mem class out of ISACaller
2021-03-09 Luke Kenneth Casso... cleanup imports
2021-03-09 Luke Kenneth Casso... move ISACaller RADIX MMU class to separate module
2021-03-09 Luke Kenneth Casso... add pgtable and pte calculation to RADIX ISACaller
2021-03-08 Luke Kenneth Casso... start adding _get_prtable_addr
2021-03-08 Luke Kenneth Casso... actually make it possible to disable svp64 on commandli...
2021-03-08 Luke Kenneth Casso... add option to cut out SVP64 from PowerDecoder2
2021-03-07 Cesar StraussFix missing NIA update on ISACaller
2021-03-07 Tobias PlatenRADIX: read SPRs
2021-03-07 Tobias PlatenRADIX: implement memassign and call
2021-03-05 Tobias Platenunit test: pass bool mmu
2021-03-05 Luke Kenneth Casso... add comments and more stub functions
2021-03-05 Luke Kenneth Casso... add segment_check function, plus quick test.
2021-03-05 Luke Kenneth Casso... add decode_prte function to RADIX
2021-03-05 Luke Kenneth Casso... add trivial LD/ST redirectors into RADIX ISACaller
2021-03-04 Luke Kenneth Casso... whitespace
2021-03-04 Tobias Platenupdate test_caller_radix.py
2021-03-04 Tobias PlatenISACaller: add option mmu
2021-03-04 Luke Kenneth Casso... whoops microwatt already allocates SPR 720
2021-03-04 Luke Kenneth Casso... add comments from gem5-experimental mmu
2021-03-04 Luke Kenneth Casso... add cached pgtbl0/3
2021-03-04 Luke Kenneth Casso... add two functions for checking permissions, to be based...
2021-03-03 Tobias Platenadd RADIX skeleton and unit test
2021-03-03 Luke Kenneth Casso... add debug strings
2021-03-03 Luke Kenneth Casso... remove singleton pattern
2021-03-02 Luke Kenneth Casso... operating correctly, not directing MMU SPRs to SPR...
2021-03-01 Luke Kenneth Casso... Revert "fix Bug 607 - unnecessary code added related...
2021-03-01 Luke Kenneth Casso... move SVP64 RM decoder to separate module
2021-02-28 Luke Kenneth Casso... start on SVP64 RM Mode decoder
2021-02-28 Luke Kenneth Casso... more SVP64 enums
2021-02-28 Luke Kenneth Casso... add SVP64 RM sub-field enums
2021-02-28 Luke Kenneth Casso... move SVP64 Extra decoders to separate module
2021-02-28 Luke Kenneth Casso... fix syntax error
2021-02-28 Luke Kenneth Casso... move SVP64PrefixDecoder to separate module
2021-02-28 Luke Kenneth Casso... add PowerDecoder.no_in_vec
2021-02-28 Luke Kenneth Casso... add svp64_instrs to power_svp64
2021-02-28 Tobias Platenfix Bug 607 - unnecessary code added related to MMU...
2021-02-28 Tobias Platenfix Bug 603 - use SPR names/numbers from sprs.csv
2021-02-27 Luke Kenneth Casso... use PowerDecoder2.no_out_vec instead of manual vector...
2021-02-27 Luke Kenneth Casso... add corresponding VL=0 unit test as from 161b7d67b...
2021-02-24 Luke Kenneth Casso... add comments explaining split
2021-02-24 Luke Kenneth Casso... move DecodeCROut/In (at last) out of PowerDecoderSubset...
2021-02-24 Luke Kenneth Casso... start making write_cr0 independent of DecodeCROut
2021-02-22 Cesar StraussFix typo when calculating PowerDecoder2.no_out_vec
2021-02-21 Luke Kenneth Casso... add CR out vector detection to PowerDecoder2 no_out_vec
2021-02-21 Cesar StraussThe new version of "sel" is smart enough to find a...
2021-02-21 Luke Kenneth Casso... comments in SVP64RMFields
2021-02-21 Cesar StraussUse the new selection field function from nmutil
2021-02-21 Cesar StraussUse symbolic values as field sizes
2021-02-21 Cesar StraussReplace all hardcoded shifts into RM by usage of SVP64R...
2021-02-21 Luke Kenneth Casso... create SVP64CROffs consts for when SVP64 Vector-of...
2021-02-20 Luke Kenneth Casso... comments on sv.add. Rc=1 unit test
2021-02-20 Luke Kenneth Casso... add in Vectorised CRs when Rc=1 into ISACaller
2021-02-20 Luke Kenneth Casso... add CR1 to DecodeCRIn/Out
2021-02-20 Luke Kenneth Casso... add some debug checking to get_pdecode_cr_out
2021-02-20 Luke Kenneth Casso... add crossreference to bug #603
2021-02-20 Luke Kenneth Casso... add more debug output to get_pdecode_cr_out
2021-02-20 Cesar StraussAssemble the SV64 prefix from its subfields using SVP64...
2021-02-20 Luke Kenneth Casso... start on CRs in SVP64 mode
2021-02-20 Cesar StraussFix more MSB0 issues in comments
2021-02-20 Cesar StraussReplace more hardcoded constants with symbolic field...
2021-02-20 Luke Kenneth Casso... increment CRs based on srcstep, see what happens
2021-02-17 Cesar StraussUse subfield bit selection to extract the RM SVP64...
2021-02-17 Cesar StraussReplace MSB-i by symbolic subfield indices and selectors
2021-02-17 Luke Kenneth Casso... fix reg read/write in ISACaller, PowerDecoder2 handles...
2021-02-16 Cesar StraussFix MSB0 issues for SVP64
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-16 Luke Kenneth Casso... ordering wrong on svstate in ISACaller
2021-02-16 Luke Kenneth Casso... add indicator to PowerDecoder2 when no outputs are...
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-14 Cesar StraussFix width of the "extra" input on the Extra decoder
2021-02-14 Cesar StraussFix conversion to MSB0
2021-02-14 Luke Kenneth Casso... add srcstep onto Vectorised GPRs in PowerDecoder2
2021-02-13 Tobias PlatenOP_TLBIE must in be instr_is_priv
2021-02-13 Tobias Platenkeep commits to under 80 chars
2021-02-13 Luke Kenneth Casso... update svp64 unit test comments
2021-02-13 Tobias Platenforward microwatt mmu specific SPR: PID and PRTBL
2021-02-12 Luke Kenneth Casso... add skip of instruction if SVSTATE.VL=0 in ISACaller
2021-02-12 Luke Kenneth Casso... validate all registers to make sure no damage occurs...
2021-02-12 Luke Kenneth Casso... add srcstep and correct PC-advancing during Sub-PC...
2021-02-12 Luke Kenneth Casso... comments
2021-02-12 Luke Kenneth Casso... add in SVSTATE.srcstep update, loop from 0 to VL-1
2021-02-12 Luke Kenneth Casso... allow PC to update by 8 in SVP64 mode
2021-02-12 Luke Kenneth Casso... fix setting of SVSTATE.VL and MVL
2021-02-12 Luke Kenneth Casso... add in SVSTATE to ISACaller, not used, just passed in
2021-02-11 Luke Kenneth Casso... comments in TestIssuer for SVP64PrefixDecoder
2021-02-10 Luke Kenneth Casso... add svp64 reg decode detection to ISACaller output
2021-02-10 Luke Kenneth Casso... starting to add SVP64 register EXTRA-read and isvec...
2021-02-10 Luke Kenneth Casso... comment update
2021-02-04 Tobias Platenpass SPR MicroOp to MMU function unit
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