Merge branch 'master' of git.libre-soc.org:soc
[soc.git] / src / soc / experiment / compalu_multi.py
2020-08-15 Luke Kenneth Casso... clear compalu data latch always on issue
2020-08-14 Luke Kenneth Casso... remove latchregister, use sync to capture compunit...
2020-08-14 Luke Kenneth Casso... sync on alu results in compalu
2020-08-13 Luke Kenneth Casso... code-shuffle
2020-08-13 Luke Kenneth Casso... sync on reset in compalu
2020-08-13 Luke Kenneth Casso... another sync to cut latency
2020-08-13 Luke Kenneth Casso... remove latchregister, sync src oper_i into MultiCompUnit
2020-08-13 Luke Kenneth Casso... minor tidyup on alu compunit:
2020-08-13 Luke Kenneth Casso... plenty of time to wait for operand, so use "sync" in...
2020-08-09 Luke Kenneth Casso... compalu combinatorial loop detected
2020-07-29 Luke Kenneth Casso... bit of a big change: add prefixes "cu_" to all CompUnit...
2020-07-25 Luke Kenneth Casso... going on a bit of a "naming" spree, this for Jean-Paul...
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-11 Luke Kenneth Casso... sort out core write latching: gate by busy, and use...
2020-07-11 Luke Kenneth Casso... * clarifying core function unit enable
2020-07-02 Luke Kenneth Casso... allow ALU names to propagate through from FU to CompUni...
2020-06-11 Luke Kenneth Casso... even more complexity in CompALUMulti, to deal with...
2020-06-09 Cesar StraussAvoid a combinatorial loop on valid_o
2020-06-06 Luke Kenneth Casso... allow Mem initialisation in ISACaller
2020-06-06 Luke Kenneth Casso... LDSTCompUnit test data structures linked up, starting...
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-02 Luke Kenneth Casso... argh - bad hack, detecting when there are no registers...
2020-06-01 Luke Kenneth Casso... sigh - another instance where write-mask needed to...
2020-05-31 Luke Kenneth Casso... remove unneeded imports
2020-05-31 Luke Kenneth Casso... split out compalu unit tests to separate module (gettin...
2020-05-31 Luke Kenneth Casso... HA! found a bug in MultiCompUnit handling of write...
2020-05-30 Luke Kenneth Casso... add in write-mask into MultiCompUnit and MCU-ALU unit...
2020-05-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-30 Luke Kenneth Casso... create a write-mask, anything with an "ok" in the Recor...
2020-05-30 Luke Kenneth Casso... allow MultiCompUnit outputs to be Records, to capture...
2020-05-30 Luke Kenneth Casso... add read-mask to MultiCompUnit
2020-05-30 Luke Kenneth Casso... code-shuffle / comments
2020-05-30 Luke Kenneth Casso... mess - but a functional mess. ALU-MultiCompUnit semi...
2020-05-30 Luke Kenneth Casso... grab other results from ALU pipeline in compunit test
2020-05-30 Luke Kenneth Casso... still experimenting with ALU-CompUnit interaction
2020-05-29 Luke Kenneth Casso... trigger ALU ready when operands ready
2020-05-29 Luke Kenneth Casso... trigger read ALU ready/valid from latch as well
2020-05-29 Luke Kenneth Casso... use a latch to communicate read/valid output from ALU
2020-05-29 Luke Kenneth Casso... latch all output on ALU output valid
2020-05-29 Luke Kenneth Casso... create read-done pulse
2020-05-29 Luke Kenneth Casso... write-release moves out of "ALU valid" due to using...
2020-05-29 Luke Kenneth Casso... signal start of request from when ALU triggers result...
2020-05-29 Luke Kenneth Casso... create rising pulse from ALU valid
2020-05-29 Luke Kenneth Casso... names of attributes needs to be dest_o not dest_i
2020-05-29 Cesar StraussAllow immediate assertion of go in the same cycle as rel
2020-05-29 Cesar StraussCorrect typo
2020-05-29 Cesar StraussSend a one-clock "go" pulse after a configurable number...
2020-05-28 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-28 Luke Kenneth Casso... add quick test of 3-operand DummyALU in MultiCompALU
2020-05-28 Luke Kenneth Casso... debugging test_alu_compunit.py
2020-05-28 Cesar StraussCheck that rd rises after issue_i, unless it's immediate
2020-05-28 Cesar StraussStore and present parameters together with issue_i
2020-05-27 Cesar StraussMove test case parameters to an "operation" member...
2020-05-27 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-27 Cesar StraussRemove the monitor process
2020-05-25 Cesar StraussCheck that busy_o doesn't rise on its own
2020-05-25 Cesar StraussImplement the issue_i/busy_o protocol check.
2020-05-25 Cesar StraussMove process list to CompUnitParallelTest
2020-05-25 Luke Kenneth Casso... update comments on compalu_multi.py
2020-05-25 Luke Kenneth Casso... add some more stub comments
2020-05-25 Luke Kenneth Casso... yield blank so test passes
2020-05-25 Luke Kenneth Casso... add stubs
2020-05-25 Luke Kenneth Casso... add comments
2020-05-25 Cesar StraussFix detection of busy_o inside the monitor process
2020-05-25 Cesar StraussProof of concept of a parallel test
2020-05-25 Luke Kenneth Casso... must not do rd-req checking when both imm and zero...
2020-05-25 Luke Kenneth Casso... comment out invalid test
2020-05-25 Luke Kenneth Casso... lots of greater than 80 chars
2020-05-25 Luke Kenneth Casso... switch out req rel if immediate enabled
2020-05-25 Cesar StraussShow oper_r and oper_i in the signal list, in simulation
2020-05-24 Luke Kenneth Casso... spelling
2020-05-24 Luke Kenneth Casso... spelling
2020-05-24 Cesar StraussAvoid overwriting the first vcd file with the second one
2020-05-24 Cesar StraussRename the internal DFF of latchregisters to avoid...
2020-05-24 Luke Kenneth Casso... move docstring to wiki for compunit
2020-05-23 Cesar StraussAdd a few test cases with zero_a set, in combination...
2020-05-23 Cesar StraussAllow zero_a to be set when simulating an operation
2020-05-23 Luke Kenneth Casso... common function for op zero and op immed
2020-05-23 Cesar StraussChoose between RA (src1) and zero immediate, conditione...
2020-05-23 Luke Kenneth Casso... add comments
2020-05-23 Luke Kenneth Casso... split out RegSpecs into separate module
2020-05-23 Luke Kenneth Casso... split out RegSpec API into separate class (TODO: move...
2020-05-23 Luke Kenneth Casso... add notes on FunctionUnit API
2020-05-23 Luke Kenneth Casso... make MultiCompUnit and testing ALU use regspec API...
2020-05-23 Luke Kenneth Casso... make demo/test ALU look like nmigen pipeline API
2020-05-23 Luke Kenneth Casso... add link to regspecs on wiki
2020-05-23 Luke Kenneth Casso... add regspec capability to MultiCompUnit
2020-05-23 Luke Kenneth Casso... make immediate-or-RA selection optional based on awaren...
2020-05-23 Luke Kenneth Casso... start to morph MultiCompUnit to take "regspec" as the...
2020-05-22 Luke Kenneth Casso... update comments for ALUCompUnit
2020-05-21 Luke Kenneth Casso... document subkls in CompUnitRecord
2020-05-21 Luke Kenneth Casso... code-morph LDSTCompUnit to use RecordObject structure...
2020-05-21 Cesar StraussFixed typo and left-over from refactoring
2020-05-20 Luke Kenneth Casso... convert CompUnit to use CompUnitRecord
2020-05-20 Luke Kenneth Casso... fix a series of random imports
2020-04-23 Luke Kenneth Casso... comment req_done
2020-04-23 Luke Kenneth Casso... hair-raising series of half-way-house changes which...
2020-04-23 Luke Kenneth Casso... rename MultiCompUnit
2020-04-22 Luke Kenneth Casso... fix request-done in compalu_multi
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