| 2022-07-06 |
Luke Kenneth Casso... | add fabric compatibility mode |
commit | commitdiff |
| 2022-06-26 |
Luke Kenneth Casso... | reduce icache/dcache TLB sizes |
commit | commitdiff |
| 2022-04-29 |
Luke Kenneth Casso... | add option to set small cache sizes in |
commit | commitdiff |
| 2022-04-16 |
Luke Kenneth Casso... | reduce dcache/icache number of ways, to fit into ECP5... |
commit | commitdiff |
| 2022-03-26 |
Luke Kenneth Casso... | rename PLRU modules to avoid conflict in microwatt |
commit | commitdiff |
| 2022-03-08 |
Luke Kenneth Casso... | remove ld_stbs_done from dcache: not needed |
commit | commitdiff |
| 2022-02-20 |
Luke Kenneth Casso... | add syn_ramstyle "block_ram" attributes and reduce... |
commit | commitdiff |
| 2022-02-18 |
Luke Kenneth Casso... | use block_ram attribute for FPGA synthesis |
commit | commitdiff |
| 2022-02-18 |
Luke Kenneth Casso... | reduce number of d-cache lines in microwatt fpga mode |
commit | commitdiff |
| 2022-02-18 |
Luke Kenneth Casso... | couple of adjustments to reduce gate count in i/d-cache |
commit | commitdiff |
| 2022-02-18 |
Luke Kenneth Casso... | reduce TLB set size from 64 to 16 to get FPGA resource... |
commit | commitdiff |
| 2022-02-16 |
Luke Kenneth Casso... | oof. big update to DCache to accept config parameters |
commit | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | fix bug in itlb_valid SRLatch set/reset, a bit weird... |
commit | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | use Memory for cache tags in dcache |
commit | commitdiff |
| 2022-01-30 |
Luke Kenneth Casso... | break out cache_tags and cache_valids (again) this... |
commit | commitdiff |
| 2022-01-29 |
Luke Kenneth Casso... | explanatory comment when page hit is the same for stores |
commit | commitdiff |
| 2022-01-29 |
Luke Kenneth Casso... | use right offset in dcache wb address |
commit | commitdiff |
| 2022-01-29 |
Luke Kenneth Casso... | re-examining dcache.vhdl, still did not get the store... |
commit | commitdiff |
| 2022-01-29 |
Luke Kenneth Casso... | bug in dcache.py where when two stores occur in the... |
commit | commitdiff |
| 2022-01-25 |
Luke Kenneth Casso... | add license and copyright header to dcache.py, |
commit | commitdiff |
| 2022-01-24 |
Luke Kenneth Casso... | comments |
commit | commitdiff |
| 2022-01-24 |
Luke Kenneth Casso... | hmm there seems to have been an error in DTLB Read, |
commit | commitdiff |
| 2022-01-23 |
Luke Kenneth Casso... | looked in soc.vhdl in microwatt and the parameters... |
commit | commitdiff |
| 2022-01-23 |
Luke Kenneth Casso... | add debug output of whether stall occurs on dcache |
commit | commitdiff |
| 2022-01-22 |
Luke Kenneth Casso... | missed setting of r0_full to zero in dcache. not encoun... |
commit | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | forgot name on dcache Reservation |
commit | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | pass over atomic signals to dcache from loadstore. |
commit | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | try using req.op in RELOAD_WAIT_ACK to detect whether... |
commit | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | workaround for bug in dcache where the r1.req waiting... ldst_misalign |
commit | commitdiff |
| 2022-01-14 |
Luke Kenneth Casso... | split out CacheTag Record to separate structure |
commit | commitdiff |
| 2022-01-14 |
Luke Kenneth Casso... | update how d_valid is handled |
commit | commitdiff |
| 2022-01-14 |
Luke Kenneth Casso... | missed setting r1.store_way and r1.store_row in STORE_W... |
commit | commitdiff |
| 2022-01-14 |
Luke Kenneth Casso... | Revert "dcache 2nd stage (r1) should only indicate... |
commit | commitdiff |
| 2022-01-12 |
Luke Kenneth Casso... | dcache 2nd stage (r1) should only indicate not-busy |
commit | commitdiff |
| 2022-01-12 |
Luke Kenneth Casso... | fix issue with d_valid in dcache, was not being set... |
commit | commitdiff |
| 2022-01-06 |
Luke Kenneth Casso... | double the number of lines in the L1 D/I-Cache to match... |
commit | commitdiff |
| 2022-01-05 |
Luke Kenneth Casso... | use microwatt-specific PLRU due to bug in nmutil version |
commit | commitdiff |
| 2022-01-03 |
Luke Kenneth Casso... | adding an extra option to issuer_verilog.py to be able... |
commit | commitdiff |
| 2021-12-26 |
Luke Kenneth Casso... | whoops, using variable RegStage0 in dcache stage_0... |
commit | commitdiff |
| 2021-12-26 |
Luke Kenneth Casso... | missed reset of d_valid in dcache.py and missed that its |
commit | commitdiff |
| 2021-12-23 |
Luke Kenneth Casso... | somehow managed to miss out setting r1.forward_valid1... |
commit | commitdiff |
| 2021-12-23 |
Luke Kenneth Casso... | uniquify names in dcache.py |
commit | commitdiff |
| 2021-12-22 |
Luke Kenneth Casso... | only use a single variable for ack adjusting in dcache.py |
commit | commitdiff |
| 2021-12-22 |
Luke Kenneth Casso... | ooo far too late at night to be doing this |
commit | commitdiff |
| 2021-12-22 |
Luke Kenneth Casso... | remove bus_ack (found bug in Simulation, sorted) |
commit | commitdiff |
| 2021-12-18 |
Luke Kenneth Casso... | sort out reset signalling after tracking down Simulatio... |
commit | commitdiff |
| 2021-12-18 |
Luke Kenneth Casso... | add icache/dcache/mmu unit test for TestIssuer |
commit | commitdiff |
| 2021-12-16 |
Luke Kenneth Casso... | whoops, a Simulation bug, dcache bus ack Signal needed... |
commit | commitdiff |
| 2021-12-07 |
Luke Kenneth Casso... | add discussion links and bugreport |
commit | commitdiff |
| 2021-12-07 |
Luke Kenneth Casso... | invert mmureq statements |
commit | commitdiff |
| 2021-12-07 |
Luke Kenneth Casso... | submodule tidyup |
commit | commitdiff |
| 2021-12-07 |
Luke Kenneth Casso... | tidyup, comments |
commit | commitdiff |
| 2021-12-07 |
Luke Kenneth Casso... | debug print |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | another major bug, CacheTagArray valid was only 1 bit... |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | tidyup: move hit_set to DCachePendingHit in dcache.py |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | dcache.py tidyup |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | rename dtlb to dtlb_valid and tidyup |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | convert TLBArray to TLBValidArray |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | convert DTLBUpdate to use a pair of Memorys |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | more signals local to DTLBUpdate |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | more signals local to DTLBUpdate |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | update DTLBUpdate to reflect internal API now |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | ooo nasty bug. used tlb_hit.way instead of tlb_hit... |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | move DTLB Tags/Valids/PTEs into DTLBUpdate module |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | start moving TLBArray into DTLBUpdate |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | PLRUs were selecting an output index, only one selected |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | repeated copies of read/write addr/sel to Cache SRAMs |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | move bank of PLRUs to their own submodule in both dcach... |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | code-comments |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | use binary-to-unary encoders in dcache.py |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | global (one) do_read signal in cache_rams dcache.py |
commit | commitdiff |
| 2021-12-06 |
Luke Kenneth Casso... | use one-hot binary-to-unary in dcache.py |
commit | commitdiff |
| 2021-12-05 |
Luke Kenneth Casso... | use unary encoding (one-hot) for replace_way hit_way... |
commit | commitdiff |
| 2021-12-05 |
Luke Kenneth Casso... | whitespace and minor cleanup of D-Cache |
commit | commitdiff |
| 2021-12-05 |
Luke Kenneth Casso... | more use of TLBHit Record in D-Cache |
commit | commitdiff |
| 2021-12-05 |
Luke Kenneth Casso... | correct tlb_hit_way and index sizes, use TLBHit Record... |
commit | commitdiff |
| 2021-12-05 |
Luke Kenneth Casso... | use TLBRecord in D-Cache for which TLB is selected |
commit | commitdiff |
| 2021-12-05 |
Luke Kenneth Casso... | split out TLBRecord, correct number of valid bits |
commit | commitdiff |
| 2021-12-05 |
Luke Kenneth Casso... | use Record in DCache for TLB |
commit | commitdiff |
| 2021-12-05 |
Luke Kenneth Casso... | use Record in D-Cache Cache Tags |
commit | commitdiff |
| 2021-12-05 |
Luke Kenneth Casso... | fix icache row store issue |
commit | commitdiff |
| 2021-12-05 |
Luke Kenneth Casso... | wishbone bus convert on dcache |
commit | commitdiff |
| 2021-11-11 |
Luke Kenneth Casso... | invert numbering on CR HDLState.get_crregs |
commit | commitdiff |
| 2021-08-24 |
Luke Kenneth Casso... | big rename, global/search/replace of ready_o with o_rea... |
commit | commitdiff |
| 2021-07-14 |
Tobias Platen | dcache: improve debug output |
commit | commitdiff |
| 2021-06-20 |
Tobias Platen | dcache: add debug output |
commit | commitdiff |
| 2021-05-13 |
Luke Kenneth Casso... | yet more debug log stuff for DCache, this time on Cache... |
commit | commitdiff |
| 2021-05-13 |
Luke Kenneth Casso... | ha, hilarious: swapped TLBUpdate output sizes db_out... |
commit | commitdiff |
| 2021-05-13 |
Luke Kenneth Casso... | whoops TLBIE must *clear* the valid bit not set it... |
commit | commitdiff |
| 2021-05-13 |
Luke Kenneth Casso... | more debug Display in dcache.py |
commit | commitdiff |
| 2021-05-13 |
Luke Kenneth Casso... | putting in a lot more debug print statements in DCache... |
commit | commitdiff |
| 2021-05-12 |
Luke Kenneth Casso... | move dcache unit test to separate test_dcache.py |
commit | commitdiff |
| 2021-05-10 |
Luke Kenneth Casso... | whoops, indentation issue on m.If/m.Else in dcache.py |
commit | commitdiff |
| 2021-05-10 |
Luke Kenneth Casso... | add links to set associative image, and bugreport |
commit | commitdiff |
| 2021-05-02 |
Luke Kenneth Casso... | add nc argument to dcache load/store tests |
commit | commitdiff |
| 2021-05-02 |
Luke Kenneth Casso... | quick hack to SRAM test and to dcache to enable classic... |
commit | commitdiff |
| 2021-05-01 |
Luke Kenneth Casso... | dcache store test: data goes in one cycle AFTER valid... |
commit | commitdiff |
| 2021-05-01 |
Cesar Strauss | Add GTKWave documents to each DCache unit test |
commit | commitdiff |
| 2021-04-26 |
Luke Kenneth Casso... | simple regression dcache test was faulty. wishbone... |
commit | commitdiff |
| 2021-04-26 |
Luke Kenneth Casso... | incorrect indentation in dcache rams |
commit | commitdiff |
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projects / soc.git / history