format code
[soc.git] / src / soc / experiment / pimem.py
2020-07-22 Jacob Lifshayformat code
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
2020-06-28 Luke Kenneth Casso... got Pi2LSUI FSM working
2020-06-28 Luke Kenneth Casso... start new version of Pi2LSUI based on PortInterfaceBase
2020-06-28 Luke Kenneth Casso... pass addr/mask through to PortInterfaceBase rd/wr addr
2020-06-28 Luke Kenneth Casso... cleanup (remove unneeded imports)
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... minor cleanup, put get/set rdport/wrport into function
2020-06-28 Luke Kenneth Casso... merge LDSTPort into TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
2020-06-26 Michael NolanMove tests for pimem to new file, add ability to test...
2020-06-26 Luke Kenneth Casso... halve the test memory size again
2020-06-26 Luke Kenneth Casso... shrink test memory size down to only 64 words
2020-06-24 Michael NolanRevert "modify PortInterface so subfields include the...
2020-06-23 Michael Nolanmodify PortInterface so subfields include the port...
2020-06-23 Luke Kenneth Casso... annoying error in latest nmigen
2020-06-22 Luke Kenneth Casso... simplified L0CacheBuffer down to a "PortInterface Arbiter"
2020-06-22 Luke Kenneth Casso... add TestMemoryPortInterface class which is designed...