Test first input port being masked out
[soc.git] / src / soc / experiment / test / test_compalu_multi.py
2020-12-31 Cesar StraussTest first input port being masked out
2020-12-31 Cesar StraussTest masked-out second input port
2020-12-31 Cesar StraussShow rdmaskn and wrmask in GTKWave
2020-12-31 Cesar StraussUse the increment operator
2020-12-31 Cesar StraussAdd support for masked write operations
2020-12-31 Cesar StraussClarify reason for holding rdmaskn valid during the...
2020-12-31 Cesar StraussRemove previous version of the CompUnit parallel unit...
2020-12-31 Cesar StraussOnly hold the decoder signals for one cycle, along...
2020-12-30 Cesar StraussTest the rdmaskn control signal
2020-12-07 Cesar StraussDisplay the instruction type as a vector on cxxsim
2020-12-06 Cesar StraussUpdate GTKWave documents to work with latest cxxsim
2020-11-24 Cesar StraussFix some typos and whitespace
2020-11-24 Cesar StraussPort the DummyALU test case to the new parallel issuer
2020-11-23 Cesar StraussResults are now a list, so "expected" should follow...
2020-11-23 Cesar StraussParameterize the issuer on the number of operands and...
2020-11-22 Cesar StraussRefactor the ALU operation issuer into a class
2020-11-22 Cesar StraussPort the ALU test case to the new parallel test style
2020-11-22 Cesar StraussAdd a GTKWave document to the ALU test case
2020-11-19 Cesar StraussSeparate input and output ports by color
2020-11-19 Cesar StraussExplain the test cases
2020-11-18 Cesar StraussSeparate individual traces for each rel_o/go_i port
2020-11-16 Cesar StraussAdd a transaction counter to producers and consumers
2020-11-15 Cesar StraussImplement ResultConsumer and port the Shifter unit...
2020-11-14 Cesar StraussMove the DUT driver to within the test case process
2020-11-14 Cesar StraussFix and enable the regspec test for the Shifter
2020-10-28 Cesar StraussImplement an operand producer that talks the rel_o...
2020-10-01 Cesar StraussAdd GTKWave document to test_compunit_fsm
2020-09-27 Cesar StraussConvert yet another few tests to be able to use latest...
2020-09-07 Luke Kenneth Casso... bit of a big reorg of data structures
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB
2020-07-29 Luke Kenneth Casso... bit of a big change: add prefixes "cu_" to all CompUnit...
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-21 Luke Kenneth Casso... testing if MultiCompUnit can handle no input regs ...
2020-07-21 Luke Kenneth Casso... disable cxxsim for now
2020-07-19 Luke Kenneth Casso... convert compalu multi test to Simulator() (was run_simu...
2020-07-19 Luke Kenneth Casso... convert compalu multi test to Simulator() (was run_simu...
2020-07-19 Luke Kenneth Casso... add some CompUnit demo tests of the alu_fsm example
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-06-28 Cesar StraussStart with a simpler test case
2020-06-09 Cesar StraussAvoid a combinatorial loop on valid_o
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Cesar StraussCheck completion of the sub-processes
2020-06-03 Cesar StraussSimplify immediate check
2020-06-03 Cesar StraussPreliminary check of the alu protocol
2020-06-03 Cesar StraussPass along the operand, in the cycle in which go is...
2020-06-02 Cesar StraussAllow at least one operand to be fetched
2020-06-02 Cesar StraussHold rdmaskn active during the busy_o cycle
2020-06-01 Cesar StraussAdd rdmaskn parameter and assert it along issue_i
2020-05-31 Luke Kenneth Casso... add comments for MultiCompUnit parallel test
2020-05-31 Luke Kenneth Casso... remove unneeded imports
2020-05-31 Luke Kenneth Casso... split out compalu unit tests to separate module (gettin...