git.libre-soc.org Git - soc.git/history - src/soc/experiment/test/test_l0_cache

2021-05-11	Luke Kenneth Casso...	pass through MSR.PR through PortInterface, into LoadStore1	blob \| commitdiff \| raw
2021-05-09	Luke Kenneth Casso...	add misalign flag to PortInterfaceBase	blob \| commitdiff \| raw \| diff to current
2020-08-24	Tobias Platen	TestCachedMemoryPortInterface cleanup	blob \| commitdiff \| raw \| diff to current
2020-08-24	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-08-21	Tobias Platen	typo fix in test_l0_cache_buffer2.py	blob \| commitdiff \| raw \| diff to current
2020-08-21	Tobias Platen	connect TestCachedMemoryPortInterface to LDSTSplitter	blob \| commitdiff \| raw \| diff to current
2020-08-21	Cole Poirier	Merge branch 'master' of git.libre-soc.org:soc	blob \| commitdiff \| raw \| diff to current
2020-08-20	Tobias Platen	start wiring TestCachedMemoryPortInterface	blob \| commitdiff \| raw \| diff to current
2020-08-20	Tobias Platen	testcase refactoring	blob \| commitdiff \| raw \| diff to current
2020-08-18	Tobias Platen	add testcase for LDSTSplitter using PortInterface	blob \| commitdiff \| raw \| diff to current
2020-08-11	Tobias Platen	initial version of L0CacheBuffer2	blob \| commitdiff \| raw \| diff to current