git.libre-soc.org Git - soc.git/history - src/soc/experiment/test/test_ldst_pi

2022-01-08	Luke Kenneth Casso...	add a second LD request to dcache which is merged with...	blob \| commitdiff \| raw
2022-01-08	Luke Kenneth Casso...	start adding in mis-aligned LD/ST support into LoadStore1	blob \| commitdiff \| raw \| diff to current
2021-12-13	Luke Kenneth Casso...	set pr=0 because privileged mode is pr=0 not pr=1	blob \| commitdiff \| raw \| diff to current
2021-12-13	Luke Kenneth Casso...	add in missing MSRSpec import	blob \| commitdiff \| raw \| diff to current
2021-12-13	Tobias Platen	update MMU PortInterface Test (misalign)	blob \| commitdiff \| raw \| diff to current
2021-12-05	Luke Kenneth Casso...	wishbone bus convert on dcache	blob \| commitdiff \| raw \| diff to current
2021-12-04	Luke Kenneth Casso...	remove yet another duplicated copy of wb_get and add...	blob \| commitdiff \| raw \| diff to current
2021-05-26	Luke Kenneth Casso...	add ldst PortInterface misalign unit test (underway)	blob \| commitdiff \| raw \| diff to current