git.libre-soc.org Git - soc.git/history - src/soc/experiment/test/test_mmu_dcache

[soc.git] / src / soc / experiment / test / test_mmu_dcache_pi.py

2022-02-23	Luke Kenneth Casso...	forgot to pass cix (cache-inhibited) through to LD...	blob \| commitdiff \| raw
2021-12-13	Tobias Platen	update old TestMicrowattMemoryPortInterface	blob \| commitdiff \| raw \| diff to current
2021-12-05	Luke Kenneth Casso...	replace yet another duplicate copy of wb_get, possible...	blob \| commitdiff \| raw \| diff to current
2021-12-05	Luke Kenneth Casso...	wishbone bus convert on dcache	blob \| commitdiff \| raw \| diff to current
2021-12-04	Luke Kenneth Casso...	rename function which needs replacing	blob \| commitdiff \| raw \| diff to current
2021-10-08	Tobias Platen	an extra dcbz parameter in all six places	blob \| commitdiff \| raw \| diff to current
2021-10-03	Tobias Platen	an extra dcbz parameter in all six places	blob \| commitdiff \| raw \| diff to current
2021-05-13	Luke Kenneth Casso...	fix wb_get error where data was being corrupted	blob \| commitdiff \| raw \| diff to current
2021-05-12	Luke Kenneth Casso...	add debug info, update comments, disable dcache in...	blob \| commitdiff \| raw \| diff to current
2021-05-12	Luke Kenneth Casso...	whoops missing default zero (no idea how)	blob \| commitdiff \| raw \| diff to current
2021-05-12	Luke Kenneth Casso...	addcomments for MMU PortInterface test (how it, um...	blob \| commitdiff \| raw \| diff to current
2021-05-12	Luke Kenneth Casso...	bit of a hack to get test_mmu_dcache_pi.py operational.	blob \| commitdiff \| raw \| diff to current
2021-05-12	Luke Kenneth Casso...	whitespace	blob \| commitdiff \| raw \| diff to current
2021-05-11	Luke Kenneth Casso...	pass through MSR.PR through PortInterface, into LoadStore1	blob \| commitdiff \| raw \| diff to current
2021-05-09	Luke Kenneth Casso...	add misalign flag to PortInterfaceBase	blob \| commitdiff \| raw \| diff to current
2020-10-06	Tobias Platen	test_mmu_dcache_pi.py	blob \| commitdiff \| raw \| diff to current

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