radix: reading first page table entry
[soc.git] / src / soc / experiment /
2021-02-24 Tobias Platenwb_get: write outputs to seperate logfile too
2021-02-20 Luke Kenneth Casso... remove massive code-duplication, move simple "self...
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-15 Cole Poirierremove file experiment/formal/proof_icache.py as it...
2021-02-09 colepoirieradd missing newline at end of experiment/formal/.gitignore
2021-02-09 colepoirierfix erroneous removal of proof* from experiment/formal...
2021-02-07 colepoirieradd skeleton implementation of experiment/formal/proof_...
2021-02-07 colepoiriericache.py fix formatting
2021-02-07 colepoirierModify experiment/formal/.gitignore because was prevent...
2021-01-10 Tobias Platenadd microwatt mmu config option to compunits.py
2021-01-01 Cesar StraussAdd zero CR test case and fix comments
2021-01-01 Cesar StraussAdd test cases with rc=1
2021-01-01 Cesar StraussMake all ports the same size, on the test ALU
2021-01-01 Cesar StraussAdd CR output port to test cases
2021-01-01 Cesar StraussAdd CR to the output data port
2021-01-01 Cesar StraussMake output write enables independent of valid_o
2021-01-01 Cesar StraussMove NOP test case earlier
2021-01-01 Cesar StraussDisable data value output on NOP
2021-01-01 Cesar StraussAdd condition register (CR) output
2020-12-31 Cesar StraussImplement and test NOP in the test ALU
2020-12-31 Cesar StraussDon't use OP_NOP for zero-delay subtraction
2020-12-31 Cesar StraussTest first input port being masked out
2020-12-31 Cesar StraussSign extend the second input port
2020-12-31 Cesar StraussTest masked-out second input port
2020-12-31 Cesar StraussAdd sign extend to the Test ALU
2020-12-31 Cesar StraussShow rdmaskn and wrmask in GTKWave
2020-12-31 Cesar StraussUse the increment operator
2020-12-31 Cesar StraussAdd support for masked write operations
2020-12-31 Cesar StraussClarify reason for holding rdmaskn valid during the...
2020-12-31 Cesar StraussRemove previous version of the CompUnit parallel unit...
2020-12-31 Cesar StraussOnly hold the decoder signals for one cycle, along...
2020-12-30 Cesar StraussTest the rdmaskn control signal
2020-12-29 Cesar StraussRemove left-over comments.
2020-12-13 Cesar StraussAllow more test cases to be run with CXXSim
2020-12-07 Cesar StraussDisplay the instruction type as a vector on cxxsim
2020-12-06 Cesar StraussUpdate GTKWave documents to work with latest cxxsim
2020-11-24 Cesar StraussFix some typos and whitespace
2020-11-24 Cesar StraussPort the DummyALU test case to the new parallel issuer
2020-11-23 Cesar StraussResults are now a list, so "expected" should follow...
2020-11-23 Cesar StraussParameterize the issuer on the number of operands and...
2020-11-22 Cesar StraussRefactor the ALU operation issuer into a class
2020-11-22 Cesar StraussPort the ALU test case to the new parallel test style
2020-11-22 Cesar StraussAdd a GTKWave document to the ALU test case
2020-11-19 Cesar StraussSeparate input and output ports by color
2020-11-19 Cesar StraussExplain the test cases
2020-11-18 Cesar StraussSeparate individual traces for each rel_o/go_i port
2020-11-16 Cesar StraussAdd a transaction counter to producers and consumers
2020-11-15 Cesar StraussImplement ResultConsumer and port the Shifter unit...
2020-11-14 Cesar StraussMove the DUT driver to within the test case process
2020-11-14 Cesar StraussFix and enable the regspec test for the Shifter
2020-11-01 Cesar StraussAdd a check for liveness.
2020-10-31 Cesar StraussCheck that the read and write counters differ at most...
2020-10-31 Cesar StraussRemove stray comment
2020-10-28 Cesar StraussImplement an operand producer that talks the rel_o...
2020-10-24 Cesar StraussCreate a GTKWave document for the test ALU unit tests
2020-10-18 Cole Poirieruse random.seed to generate repro cases of the two...
2020-10-12 Cole Poirierfix ModuleNotFound/Import errors found when running...
2020-10-08 Luke Kenneth Casso... minor icache cleanup
2020-10-08 Cole Poiriersecond attempt at https://bugs.libre-soc.org/show_bug...
2020-10-08 Cole Poirierremove singleton dict per https://bugs.libre-soc.org...
2020-10-08 Cole Poirierfirst attempt at 3) of
2020-10-08 Cole Poiriermodify wb_get per 1) of https://bugs.libre-soc.org...
2020-10-07 Tobias Platenconnect mmu_done, ldst_error, cache_paradox
2020-10-06 Tobias Platenremove redunant signals
2020-10-06 Luke Kenneth Casso... update comments on pimem.py
2020-10-06 Tobias Platentest_mmu_dcache_pi.py
2020-10-06 Luke Kenneth Casso... passing LDSTException over to Trap Pipeline
2020-10-06 Luke Kenneth Casso... make LDSTException fields added from list of fieldnames
2020-10-06 Luke Kenneth Casso... move LDSTException to mem_types
2020-10-06 Luke Kenneth Casso... add LDSTException to PortInterface
2020-10-05 Luke Kenneth Casso... add debug / investigation print statements
2020-10-05 Cole Poiriericache.py fix ispow2() util fn per https://bugs.libre...
2020-10-05 Luke Kenneth Casso... whoops fix syntax error
2020-10-05 Luke Kenneth Casso... whoops fix syntax error
2020-10-05 Luke Kenneth Casso... return test rather than "if test return True else False"
2020-10-05 Luke Kenneth Casso... whitespace
2020-10-05 Luke Kenneth Casso... whitespace
2020-10-05 Cole Poiriericache.py add python asserts that were a TODO commented...
2020-10-05 Cole Poiriericache.py fix formatting, mostly due to reduced indenta...
2020-10-05 Cole Poiriericache.py remove comment that contained the entirety...
2020-10-05 Cole Poiriericache.py move icache_miss WAIT_ACK FSM state into...
2020-10-05 Cole Poiriericache.py move icache_miss CLR_TAG FSM state into metho...
2020-10-05 Cole Poiriericache.py move icache_miss IDLE FSM state into method...
2020-10-02 Cole Poiriericache.py add req_hit_way as arg to icache_comb, actual...
2020-10-01 Cole Poiriericache.py add missing comb signal assignments per https...
2020-10-01 Luke Kenneth Casso... arg CacheRam read output needs delay by 1 cycle
2020-10-01 Luke Kenneth Casso... do not pass cache row array around, just the current row
2020-10-01 Luke Kenneth Casso... revert bug in icache wishbone ack
2020-10-01 Cesar StraussAdd GTKWave document to test_compunit_fsm
2020-09-30 Luke Kenneth Casso... clean up row store and wb adr in icache
2020-09-30 Luke Kenneth Casso... hmm only set wishbone address if ack is actually received
2020-09-30 Luke Kenneth Casso... add more debug prints in icache
2020-09-30 Luke Kenneth Casso... remove more reviewed comments
2020-09-30 Luke Kenneth Casso... remove reviewed comments
2020-09-30 Luke Kenneth Casso... comb on wr_index not sync
2020-09-30 Luke Kenneth Casso... start removing reviewed comments
2020-09-30 Luke Kenneth Casso... use same constant name (confusing otherwise)
2020-09-30 Luke Kenneth Casso... need asserts
2020-09-30 Luke Kenneth Casso... halve the number of icache lines for now
2020-09-30 Luke Kenneth Casso... use Repl rather than for-loop to copy bit
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