radix: reading first page table entry
[soc.git] / src / soc / experiment /
2020-09-30 Luke Kenneth Casso... move loop invariant test out of loop
2020-09-30 Luke Kenneth Casso... reduce size of ilang file by a factor of FIVE
2020-09-30 Luke Kenneth Casso... store tag in temp signal
2020-09-30 Luke Kenneth Casso... reduce gate usage by getting cache row only not entire...
2020-09-30 Luke Kenneth Casso... fix read_tag to use word_select correctly
2020-09-30 Luke Kenneth Casso... forgot to add PLRUs as submodules
2020-09-29 Cole Poiriericache.py fix combinatorial loop with by testing temp...
2020-09-29 Cole Poiriericache.py fix is_last_row_addr, get_next_row_addr
2020-09-29 Cole Poiriericache.py trying to sort out test failure, added r...
2020-09-29 Cole Poiriericache.py fix test stbs_done signal, not stbs_zero...
2020-09-29 Cole Poiriericache.py fix rarange
2020-09-29 Cole Poiriericache.py fixed numerous bugs as specified by lkcl...
2020-09-28 Cole Poiriericache.py use d_out as input to assignment instead...
2020-09-27 Cole Poiriericache.py fix translation mistake
2020-09-27 Cesar StraussConvert yet another few tests to be able to use latest...
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-25 Cole Poiriericache.py fix several subtle bugs that were lines that...
2020-09-25 Cole Poirierwb_types.py add reset value of 0b11111111 for WBSelType...
2020-09-24 Cole Poiriericache.py add some missing lines from icache.vhdl,...
2020-09-24 Cole Poiriermem_types.py wb_types.py add name constructor to all...
2020-09-24 Cole Poiriericache.py fixed all errors that raised python exception...
2020-09-24 Cesar StraussFix whitespace, remove unused imports
2020-09-24 Luke Kenneth Casso... brackets round imports looks cleaner?
2020-09-24 Cesar StraussUse nmutil simulator module to simplify choosing among...
2020-09-22 Cesar StraussPort soc.experiment.alu_fsm to the new way of invoking...
2020-09-20 Cesar StraussAdd induction proof for the FSM Shifter
2020-09-20 Cesar StraussAdd bounded proof to FSM Shifter
2020-09-20 Cesar StraussLet the formal engine create some test cases for the...
2020-09-20 Luke Kenneth Casso... resolve issues in async sim: must not drive async clock...
2020-09-20 Luke Kenneth Casso... still experimenting with async FF sync
2020-09-20 Luke Kenneth Casso... continuing async clock experimenting
2020-09-20 Luke Kenneth Casso... add an async clock synchronizer experiment
2020-09-20 Luke Kenneth Casso... first version code-morph on dmi2jtag
2020-09-19 Cesar StraussRemove demonstration code
2020-09-16 Cole Poiriercomplete first translation pass of dmi_dtm_xilinx.vhdl...
2020-09-16 Cole Poirierinitial commit of JTAGToDMI debug interface translated...
2020-09-15 Luke Kenneth Casso... comment mmu test
2020-09-15 Luke Kenneth Casso... add set MTSPR prtbl to mmu unit test
2020-09-15 Luke Kenneth Casso... add extra "modes" to PortInterface
2020-09-15 Luke Kenneth Casso... syntax error correction
2020-09-15 Luke Kenneth Casso... add inline comments into icache.py
2020-09-14 Cole Poiriericache.py add missing funciton bodies, add missing...
2020-09-14 Luke Kenneth Casso... increase TLB_NUM_WAYS to 4
2020-09-14 Luke Kenneth Casso... vhdl conversion not really working for plru
2020-09-14 Luke Kenneth Casso... add array signal names
2020-09-14 Luke Kenneth Casso... rename plru input
2020-09-14 Luke Kenneth Casso... rename plru input
2020-09-14 Luke Kenneth Casso... reorg mmu lookup test so it is called twice
2020-09-14 Luke Kenneth Casso... TLB PLRUs are of TLB_WAY_BITS width
2020-09-14 Luke Kenneth Casso... fix mmu perms/lookup in dcache
2020-09-14 Luke Kenneth Casso... whitespace
2020-09-14 Luke Kenneth Casso... remove duplicated signal
2020-09-14 Luke Kenneth Casso... comments on icache
2020-09-14 Luke Kenneth Casso... get rid of rst
2020-09-14 Luke Kenneth Casso... use word_select
2020-09-14 Luke Kenneth Casso... add mmu-dcache test
2020-09-14 Cole Poiriericache.py connect up all the sub-functions, fix typos...
2020-09-14 Cole Poiriericache.py add parameters to 'process' functions, fix...
2020-09-13 Cole Poiriericache.py move get/read/write functions out of ICache...
2020-09-13 Cole Poiriericache.py copy simulation code from dcache.py, fix...
2020-09-13 Cole Poiriericache.py fix syntax, move all constants and Array...
2020-09-13 Cole Poiriericache.py fix syntax errors that occured when running...
2020-09-13 Luke Kenneth Casso... dcache truncate wishbone address, store real_addr in...
2020-09-13 Luke Kenneth Casso... last mmu get seems ok
2020-09-13 Luke Kenneth Casso... whoops recursion error v.shift calculated from v.shift
2020-09-13 Luke Kenneth Casso... more experimenting with mmu READ_WAIT state
2020-09-13 Luke Kenneth Casso... radix tree wait error, investigating
2020-09-13 Luke Kenneth Casso... mmu test starting to make sense
2020-09-13 Luke Kenneth Casso... floundering around with MMU unit test, no idea what...
2020-09-13 Luke Kenneth Casso... mmu code-morph
2020-09-13 Luke Kenneth Casso... code-morph, add masked function
2020-09-13 Luke Kenneth Casso... move code to mmu_0
2020-09-13 Luke Kenneth Casso... add example radix walk from power-gem5
2020-09-13 Luke Kenneth Casso... MMU test
2020-09-13 Luke Kenneth Casso... sort out ariane PLRU, rename/clarify
2020-09-13 Luke Kenneth Casso... minor error in plru
2020-09-13 Luke Kenneth Casso... rename cache_valid_bits to cache_validsg
2020-09-13 Luke Kenneth Casso... cache_valid_idx too large in dcache
2020-09-13 Luke Kenneth Casso... whoops, cache valid array too small in dcache
2020-09-12 Luke Kenneth Casso... more dcache debugging
2020-09-12 Luke Kenneth Casso... missing reservation address comparison
2020-09-12 Luke Kenneth Casso... dcache tidyup
2020-09-12 Luke Kenneth Casso... more dcache debugging
2020-09-12 Luke Kenneth Casso... add random dcache mem test
2020-09-12 Luke Kenneth Casso... cache valid corrupted: fixed
2020-09-12 Luke Kenneth Casso... adding names to array signals
2020-09-12 Luke Kenneth Casso... whoops, indentation error
2020-09-12 Luke Kenneth Casso... enable Display debugs
2020-09-12 Luke Kenneth Casso... set bytesel in dcache store
2020-09-11 Luke Kenneth Casso... separat stbs_done into ld/st
2020-09-11 Luke Kenneth Casso... dcache load/store test
2020-09-11 Luke Kenneth Casso... debugging dcache
2020-09-11 Luke Kenneth Casso... wrong width for data / addr
2020-09-11 Luke Kenneth Casso... connect up WB SRAM to dcache test
2020-09-11 Luke Kenneth Casso... start on dcache test
2020-09-11 Luke Kenneth Casso... missing comb +=
2020-09-11 Luke Kenneth Casso... missing maybe_tlb_plrus
2020-09-11 Luke Kenneth Casso... WAY_BITS not TLB_WAY_BITS
2020-09-11 Luke Kenneth Casso... whoops new node not to be calculated at end
2020-09-11 Luke Kenneth Casso... try to get better DTLBUpdate
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