add OP_SC
[soc.git] / src / soc / experiment /
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Cesar StraussStart with a simpler test case
2020-06-28 Cesar StraussLet p.ready_o be active while the test ALU is idle
2020-06-28 Cesar StraussAdd missing ports to the test ALU
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... add Config Fetch interface and quick unit test
2020-06-28 Luke Kenneth Casso... add test instruction memory
2020-06-28 Luke Kenneth Casso... add readonly option to TestMemory
2020-06-28 Luke Kenneth Casso... got Pi2LSUI FSM working
2020-06-28 Luke Kenneth Casso... new Pi2LSUI working, using PortInterfaceBase
2020-06-28 Luke Kenneth Casso... start new version of Pi2LSUI based on PortInterfaceBase
2020-06-28 Luke Kenneth Casso... pass addr/mask through to PortInterfaceBase rd/wr addr
2020-06-28 Luke Kenneth Casso... cleanup (remove unneeded imports)
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... minor cleanup, put get/set rdport/wrport into function
2020-06-28 Luke Kenneth Casso... merge LDSTPort into TestMemoryPortInterface
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-28 Luke Kenneth Casso... use PortInterface connect_port
2020-06-28 Luke Kenneth Casso... attempt to get Pi2LSUI FSM working
2020-06-27 Luke Kenneth Casso... only activate ld_in_progress if addr is ok
2020-06-27 Luke Kenneth Casso... increase (double) address width in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... unit test in l0_cache to connect to testpi and test_bare_wb
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
2020-06-27 Luke Kenneth Casso... use ConfigMemoryPortInterface in TstL0CacheBuffer
2020-06-27 Luke Kenneth Casso... fix TestMemLoadStoreUnit, it required a FSM to monitor...
2020-06-27 Luke Kenneth Casso... add wishbone Pi2LSUI test
2020-06-27 Luke Kenneth Casso... reconfigureable PortInterface testing now possible
2020-06-26 Luke Kenneth Casso... name issue in Pi2LSUI
2020-06-26 Luke Kenneth Casso... slight reorg on test_pi2ls.py
2020-06-26 Luke Kenneth Casso... correct address in pi2ls
2020-06-26 Luke Kenneth Casso... oops forgot to initialise base class of TestMemLoadStor...
2020-06-26 Luke Kenneth Casso... add in LenExpand shift/mask
2020-06-26 Luke Kenneth Casso... add quick test showing Pi2LSUI not quite reading/writing to
2020-06-26 Luke Kenneth Casso... remove extraneous yields
2020-06-26 Michael NolanModify pi2ls so it passes the portinterface unit tests
2020-06-26 Luke Kenneth Casso... set address ok and fix unit test to check it properly
2020-06-26 Luke Kenneth Casso... add pi.busy_o connection, increase to 64 bit
2020-06-26 Luke Kenneth Casso... unit test broken is ok :)
2020-06-26 Luke Kenneth Casso... set pi.ld.ok to 1 if pi.is_ld_i is set
2020-06-26 Michael NolanMove tests for pimem to new file, add ability to test...
2020-06-26 Luke Kenneth Casso... whitespace
2020-06-26 Luke Kenneth Casso... halve the test memory size again
2020-06-26 Luke Kenneth Casso... shrink test memory size down to only 64 words
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-25 Luke Kenneth Casso... allow Pi2LSUI to accept incoming PortInterface and...
2020-06-25 Luke Kenneth Casso... add extra parameter, mask_wid, to TestMemLoadStoreUnit
2020-06-25 Luke Kenneth Casso... start connecting up Pi2LSUI
2020-06-25 Luke Kenneth Casso... add LenExpand module, tidyup on docstring
2020-06-25 Luke Kenneth Casso... add beginnings of Pi2LSUI
2020-06-25 Luke Kenneth Casso... add attempt at mapping between PortInterface and LoadSt...
2020-06-25 Luke Kenneth Casso... rename LoadStoreInterface signals to include _i and...
2020-06-25 Luke Kenneth Casso... whitespace
2020-06-24 Michael NolanRevert "modify PortInterface so subfields include the...
2020-06-24 Michael NolanHave lsmem handle stall and valid signals correctly
2020-06-24 Michael NolanAdd handling of byte reads and writes
2020-06-24 Michael NolanAdd more complete testbench for lsmem.py
2020-06-24 Michael NolanSuper basic first try of testmem with load store unit...
2020-06-24 Luke Kenneth Casso... import minerva and use LoadStoreUnitInterface
2020-06-24 Michael NolanAdd specification for load store interface
2020-06-23 Michael Nolanmodify PortInterface so subfields include the port...
2020-06-23 Luke Kenneth Casso... annoying error in latest nmigen
2020-06-22 Luke Kenneth Casso... remove unused module
2020-06-22 Luke Kenneth Casso... simplified L0CacheBuffer down to a "PortInterface Arbiter"
2020-06-22 Luke Kenneth Casso... add TestMemoryPortInterface class which is designed...
2020-06-22 Luke Kenneth Casso... comments for LDST CompUnit test
2020-06-22 Luke Kenneth Casso... enable byte-reverse in CompLDSTUnit test
2020-06-22 Luke Kenneth Casso... remove CompLDSTOpSubset, replace with just data_len.
2020-06-22 Luke Kenneth Casso... move BE/LE byte-reverse into LDSTCompUnit
2020-06-19 Luke Kenneth Casso... add TODO comments to upgrade L0CacheBuffer to a new...
2020-06-16 Luke Kenneth Casso... set up a TestIssuer class with a FSM for doing instruct...
2020-06-16 Luke Kenneth Casso... add ports to TestMemory
2020-06-14 Luke Kenneth Casso... add in byte-reverse from op PowerDecode2 field
2020-06-14 Luke Kenneth Casso... error in address width (truncated) in setting up L0Cach...
2020-06-14 Luke Kenneth Casso... error in naming that ended up in gtkwave from a proxy
2020-06-14 Luke Kenneth Casso... add byte-reversal on LD and ST in L0CacheBuffer
2020-06-13 Cesar StraussWait for all active rel signals to be high, and only...
2020-06-11 Luke Kenneth Casso... some ugly hacks that get LD/ST immediate working
2020-06-11 Luke Kenneth Casso... even more complexity in CompALUMulti, to deal with...
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Luke Kenneth Casso... rename unit test function in ld/st compalu_multi
2020-06-10 Luke Kenneth Casso... hmmm very confused about LD/ST CompUnit unit test
2020-06-10 Luke Kenneth Casso... wrong data structure being imported, duplicate CompLDST...
2020-06-10 Luke Kenneth Casso... remove old code
2020-06-10 Luke Kenneth Casso... set data_len in compldst_multi unit test
2020-06-10 Luke Kenneth Casso... yield ports from data_o and addr_o
2020-06-10 Luke Kenneth Casso... expand LenExpand to 4 bits in order to cover 1/2/4...
2020-06-10 Luke Kenneth Casso... got L0CacheBuffer shift/mask working on a preliminary...
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Luke Kenneth Casso... add use of classes in L0Cache unit tests
2020-06-10 Luke Kenneth Casso... start using unittest suite in l0_cache.py
2020-06-10 Luke Kenneth Casso... add in LenExpander to L0CacheBuffer, not used yet
2020-06-10 Tobias Platenmake resetless for all signals in DataMergerRecord
2020-06-09 Cesar StraussKeep the sequencer in the "done" state until ready_i...
2020-06-09 Luke Kenneth Casso... rename truncaddr to splitaddr, return LSBs and MSBs
2020-06-09 Luke Kenneth Casso... add len-expander to L0CacheBuffer, so as to be able...
2020-06-09 Tobias Platenundo code removed by commit 12297566322355ce5fed2e2a546...
2020-06-09 Tobias Platenelaborate function for DualPortSplitter
2020-06-09 Cesar StraussAvoid a combinatorial loop on valid_o
2020-06-09 Tobias Platenfixes for DualPortSplitter
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