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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
fu
/
alu
/
formal
/
proof_main_stage.py
2021-12-09
Jacob Lifshay
add parent_pspec everywhere
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2021-12-09
Jacob Lifshay
format code
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2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
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2020-07-15
Luke Kenneth Casso...
use Record Assert and also check muxid
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2020-07-12
Luke Kenneth Casso...
rename InternalOp to MicrOp
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2020-06-04
Luke Kenneth Casso...
use copy of FHDLTestCase
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2020-05-31
Luke Kenneth Casso...
OP_CMPEQB also requesting change of output reg (stop...
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2020-05-31
Luke Kenneth Casso...
OP_CMP is requesting a change of the output register...
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2020-05-27
Luke Kenneth Casso...
check cr0, ov and ca ok signals in ALU main_stage proof
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2020-05-27
Luke Kenneth Casso...
add links to bugreports into ALu formal proof as well
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2020-05-27
Luke Kenneth Casso...
add links to bugreports into alu output stage proof
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2020-05-27
Michael Nolan
Fix bug in alu main stage proof
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2020-05-24
Luke Kenneth Casso...
convert ALU to output Data on int reg
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2020-05-24
Luke Kenneth Casso...
cleanup/code-munge on ALU main stage proof
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2020-05-22
Luke Kenneth Casso...
covert ALU FU to CommonInputStage
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2020-05-20
Michael Nolan
Use overflow definition from microwatt
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2020-05-20
Michael Nolan
Add overflow handling and proof
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2020-05-20
Michael Nolan
Fix bug introduced in rebase
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2020-05-20
Luke Kenneth Casso...
update to new names for XER fields
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2020-05-20
Luke Kenneth Casso...
whitespace, rename ilang to alu_main_stage.il
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2020-05-20
Michael Nolan
Add proof for OP_CMP and OP_CMPEQB
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2020-05-20
Michael Nolan
Add proof for OP_EXTS
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2020-05-20
Michael Nolan
Add 32 bit carry handling to alu
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2020-05-18
Luke Kenneth Casso...
mass-rename of modules to soc.fu.*
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2020-05-18
Luke Kenneth Casso...
rename pipe to fu
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