add dummy call to simrun and end_test()
[soc.git] / src / soc / fu / alu / pipe_data.py
2021-05-04 Luke Kenneth Casso... rename IntegerData to FUBaseData
2020-06-06 Luke Kenneth Casso... remove unneeded imports
2020-06-06 Luke Kenneth Casso... noticed the regular pattern in all pipe_data.py (regspecs).
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... remove rdflags in pipe_data.py (redundant)
2020-06-02 Luke Kenneth Casso... rename regspecs to give a consistent naming scheme
2020-06-01 Luke Kenneth Casso... okaaay add a "rdflags" function which obtains the yes...
2020-05-24 Luke Kenneth Casso... output registers need to be Data type (consistently)
2020-05-21 Luke Kenneth Casso... move common functionality between PipeSpecs to soc...
2020-05-21 Luke Kenneth Casso... move FU IntegerData to directory below
2020-05-21 Luke Kenneth Casso... convert to individual PipeSpecs for each pipeline
2020-05-21 Luke Kenneth Casso... add regspec to ALUPipeSpec
2020-05-20 Luke Kenneth Casso... add register specs to pipeline in/out so that they...
2020-05-20 Luke Kenneth Casso... normalise XER regs carry/32 and SO
2020-05-20 Luke Kenneth Casso... convert alu output to use Data for XER and CR0
2020-05-18 Luke Kenneth Casso... mass-rename of modules to soc.fu.*
2020-05-18 Luke Kenneth Casso... rename pipe to fu