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[soc.git]
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src
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soc
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fu
/
alu
/
test
/
test_pipe_caller.py
2020-07-22
Jacob Lifshay
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2020-07-21
Luke Kenneth Casso...
whitespace
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2020-07-21
Luke Kenneth Casso...
make cxxsim optional and print warning
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2020-07-19
Luke Kenneth Casso...
use same write_vcd for cxxsim as pysim
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2020-07-19
Luke Kenneth Casso...
fix bug in alu_fsm.py found by cxxsim: missing one...
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2020-07-14
Luke Kenneth Casso...
attempting running cxxsim on ALU pipeline test
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2020-07-12
Luke Kenneth Casso...
rename InternalOp to MicrOp
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2020-07-11
Luke Kenneth Casso...
sorting out bigendian/littleendian including in qemu
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-05
Luke Kenneth Casso...
big reorg on PowerDecoder2, actually Decode2Execute1Type
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2020-06-11
Luke Kenneth Casso...
read and write version of get_sim_xer_ca are different
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2020-06-11
Luke Kenneth Casso...
rename get_sim_cr_a to get_wr_sim_cr_a for now
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2020-06-10
Luke Kenneth Casso...
use sim-get helpers in ALU input fetch
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2020-06-10
Luke Kenneth Casso...
continue ALUHelpers check alu outputs code-morph
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2020-06-10
Luke Kenneth Casso...
code-morph ALU output test check phase
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2020-06-10
Luke Kenneth Casso...
code-munge test_pipe_caller for ALU,
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2020-06-08
Luke Kenneth Casso...
more verbose debug information tracking down SO/OV...
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2020-06-08
Luke Kenneth Casso...
added check which shows that OV32 in "adde." is not...
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2020-06-07
Luke Kenneth Casso...
add extra missing args to ISA setup in alu test_pipe_caller
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2020-06-04
Luke Kenneth Casso...
no global variables in test suites
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2020-06-04
Luke Kenneth Casso...
use common TestCase in alu
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2020-06-04
Luke Kenneth Casso...
use copy of FHDLTestCase
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2020-06-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-06-03
Luke Kenneth Casso...
reorganise ALU tests, move get_cu_inputs function to...
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2020-06-03
Luke Kenneth Casso...
attempt to make carry-in and overflow-enable optional...
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2020-06-01
Luke Kenneth Casso...
RS moved to port 1 (from port 3), remove need in ALU...
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2020-05-31
Luke Kenneth Casso...
still investigating
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2020-05-31
Luke Kenneth Casso...
start with zero, try not to compare against 9 bytes...
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2020-05-31
Luke Kenneth Casso...
add in more CR debug statements
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2020-05-30
Luke Kenneth Casso...
select CR0 write out only when RC=1
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2020-05-24
Luke Kenneth Casso...
convert ALU to output Data on int reg
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2020-05-23
Luke Kenneth Casso...
remove unneeded imports
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2020-05-21
Luke Kenneth Casso...
move common functionality between PipeSpecs to soc...
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2020-05-21
Luke Kenneth Casso...
convert to individual PipeSpecs for each pipeline
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2020-05-20
Luke Kenneth Casso...
normalise XER regs carry/32 and SO
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2020-05-20
Michael Nolan
Add 32 bit carry handling to alu
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2020-05-20
Luke Kenneth Casso...
output ilang for ALU to unique file
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2020-05-20
Luke Kenneth Casso...
convert alu output to use Data for XER and CR0
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2020-05-19
Michael Nolan
Handle carry out in alu
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2020-05-18
Luke Kenneth Casso...
mass-rename of modules to soc.fu.*
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2020-05-18
Luke Kenneth Casso...
rename pipe to fu
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