format code
[soc.git] / src / soc / fu / alu / test / test_pipe_caller.py
2020-07-22 Jacob Lifshayformat code
2020-07-21 Luke Kenneth Casso... whitespace
2020-07-21 Luke Kenneth Casso... make cxxsim optional and print warning
2020-07-19 Luke Kenneth Casso... use same write_vcd for cxxsim as pysim
2020-07-19 Luke Kenneth Casso... fix bug in alu_fsm.py found by cxxsim: missing one...
2020-07-14 Luke Kenneth Casso... attempting running cxxsim on ALU pipeline test
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-06-11 Luke Kenneth Casso... read and write version of get_sim_xer_ca are different
2020-06-11 Luke Kenneth Casso... rename get_sim_cr_a to get_wr_sim_cr_a for now
2020-06-10 Luke Kenneth Casso... use sim-get helpers in ALU input fetch
2020-06-10 Luke Kenneth Casso... continue ALUHelpers check alu outputs code-morph
2020-06-10 Luke Kenneth Casso... code-morph ALU output test check phase
2020-06-10 Luke Kenneth Casso... code-munge test_pipe_caller for ALU,
2020-06-08 Luke Kenneth Casso... more verbose debug information tracking down SO/OV...
2020-06-08 Luke Kenneth Casso... added check which shows that OV32 in "adde." is not...
2020-06-07 Luke Kenneth Casso... add extra missing args to ISA setup in alu test_pipe_caller
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... use common TestCase in alu
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... reorganise ALU tests, move get_cu_inputs function to...
2020-06-03 Luke Kenneth Casso... attempt to make carry-in and overflow-enable optional...
2020-06-01 Luke Kenneth Casso... RS moved to port 1 (from port 3), remove need in ALU...
2020-05-31 Luke Kenneth Casso... still investigating
2020-05-31 Luke Kenneth Casso... start with zero, try not to compare against 9 bytes...
2020-05-31 Luke Kenneth Casso... add in more CR debug statements
2020-05-30 Luke Kenneth Casso... select CR0 write out only when RC=1
2020-05-24 Luke Kenneth Casso... convert ALU to output Data on int reg
2020-05-23 Luke Kenneth Casso... remove unneeded imports
2020-05-21 Luke Kenneth Casso... move common functionality between PipeSpecs to soc...
2020-05-21 Luke Kenneth Casso... convert to individual PipeSpecs for each pipeline
2020-05-20 Luke Kenneth Casso... normalise XER regs carry/32 and SO
2020-05-20 Michael NolanAdd 32 bit carry handling to alu
2020-05-20 Luke Kenneth Casso... output ilang for ALU to unique file
2020-05-20 Luke Kenneth Casso... convert alu output to use Data for XER and CR0
2020-05-19 Michael NolanHandle carry out in alu
2020-05-18 Luke Kenneth Casso... mass-rename of modules to soc.fu.*
2020-05-18 Luke Kenneth Casso... rename pipe to fu