move pc_i and svstate_i inside if self.run_hdl
[soc.git] / src / soc / fu / alu /
2021-08-30 Luke Kenneth Casso... fix ready/valid i/o prefix in ALU test
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-05-05 Luke Kenneth Casso... put sv_input_record_layout onto CompOpSubsetBase after all
2021-05-05 Luke Kenneth Casso... add SVP64 RM fields to ALU input record
2021-05-04 Luke Kenneth Casso... rename IntegerData to FUBaseData
2021-04-23 Luke Kenneth Casso... move ALU test cases to openpower.test
2021-04-23 Luke Kenneth Casso... import from openpower.endian
2021-04-23 Luke Kenneth Casso... use openpower.test.common
2021-04-23 Luke Kenneth Casso... correct migration of openpower-isa
2021-04-23 Luke Kenneth Casso... more openpower import conversion
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-04-21 Cesar StraussAdd CR predication test case for TestIssuer
2021-04-10 Cesar StraussAdd 1<<r3 test cases to TestIssuer
2021-04-06 Cesar StraussAdd a HDL test case, where we start at the middle of...
2021-04-03 Cesar StraussFix typo
2021-04-03 Cesar StraussAdd test case with all mask bits equal to zero
2021-04-03 Cesar StraussAdd a test case for integer single predication
2021-04-03 Cesar StraussEnable remaining disabled test cases
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-30 Cesar StraussEnable VCOMPRESS test case
2021-03-30 Cesar StraussAdd new twin predication case
2021-03-30 Cesar StraussAdjust twin predication cases for the new syntax
2021-03-22 Cesar StraussAdd test cases for integer VCOMPRESS and VEXPAND
2021-03-21 Luke Kenneth Casso... adjust syntax of SVP64 predicate test cas
2021-03-21 Luke Kenneth Casso... naah. back to "sv." syntax for SVP64 assembly
2021-03-21 Cesar StraussAdd predication test case, initially disabled
2021-03-14 Luke Kenneth Casso... remove "sv." and replace with "sv" in all SVP64Asm
2021-03-11 Cesar StraussBring a few test cases from test_caller_64.py
2021-03-11 Cesar StraussTest case for two successive SV instructions
2021-03-09 Cesar StraussEnable VL==0 vector instruction skip test case
2021-03-08 Luke Kenneth Casso... correct comments in sv.add rc=1
2021-03-07 Luke Kenneth Casso... add Rc=1 SVP64 unit test to svp64_cases.py
2021-03-06 Cesar StraussEnable the Simple-V loop test case
2021-02-26 Cesar StraussAdd a vector case with VL == 0
2021-02-17 Cesar StraussAdd a case for checking the EXTRA field and register...
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-13 Cesar StraussSkip vector test case, and add a scalar case
2021-02-13 Cesar StraussFix imports and whitespace
2021-02-13 Luke Kenneth Casso... add SVP64 TestIssuer separate unit test
2021-02-12 Luke Kenneth Casso... add one SVP64 ALU test case to get started
2021-01-31 Luke Kenneth Casso... adjusting ISACaller unit test to use ISACaller.setup_one()
2020-10-16 Luke Kenneth Casso... add LGPLv3+ notice and add copyright holders
2020-10-06 Luke Kenneth Casso... use pdecode2.do not pdecode2.e in test_pipe_caller...
2020-09-26 Luke Kenneth Casso... fix annoying alu test_pipe_caller bug, missing asmcode
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-07 Luke Kenneth Casso... bit of a big reorg of data structures
2020-09-02 Luke Kenneth Casso... fix bug in cmpli (and cmplw)
2020-09-02 Luke Kenneth Casso... bug in carry32 handling in OP_CMP
2020-09-02 Luke Kenneth Casso... add cmpl regression test (one binary, one assembly)
2020-09-02 Luke Kenneth Casso... add cmpl microwatt 1.bin test, cmpl
2020-08-30 Luke Kenneth Casso... redo OP_CMP based on microwatt. L=1 had been ignored
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... xer so is not being passed through to CR0
2020-08-27 Luke Kenneth Casso... augment addme test case to show bug #476
2020-08-27 Luke Kenneth Casso... add addze and addme uni tests
2020-08-27 Luke Kenneth Casso... reorg of SO handling related to CR0
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-23 Michael NolanAdd copyright to files in fu/ that I was the primary...
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB
2020-08-22 Luke Kenneth Casso... add regression test for nonzero addis
2020-08-22 Luke Kenneth Casso... r0 zero tests on addis, fails
2020-08-17 Luke Kenneth Casso... fix signed variants of cmp in alu
2020-08-17 Luke Kenneth Casso... add new cmp test for alu
2020-08-16 Luke Kenneth Casso... attempting to track down bug in litex bios memtest
2020-08-14 Luke Kenneth Casso... divide alu pipeline into 2 (simple last)
2020-07-29 Luke Kenneth Casso... move actual ALU test out of subTest indentation just...
2020-07-29 Jacob Lifshayclean up alu test_pipe_caller
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-29 Jacob Lifshayformat some tests
2020-07-26 Luke Kenneth Casso... convert ALU to new accumulator style
2020-07-25 Luke Kenneth Casso... add spec page numbers to logical ops
2020-07-25 Luke Kenneth Casso... add page-number comments to ALU main_stage
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-21 Luke Kenneth Casso... whitespace
2020-07-21 Luke Kenneth Casso... make cxxsim optional and print warning
2020-07-19 Luke Kenneth Casso... use same write_vcd for cxxsim as pysim
2020-07-19 Luke Kenneth Casso... fix bug in alu_fsm.py found by cxxsim: missing one...
2020-07-15 Luke Kenneth Casso... use Record Assert and also check muxid
2020-07-14 Luke Kenneth Casso... reduce code size by using CompOpSubsetBase for ALU...
2020-07-14 Luke Kenneth Casso... attempting running cxxsim on ALU pipeline test
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-09 Luke Kenneth Casso... also set so only if OE requires it
2020-07-09 Luke Kenneth Casso... whoops test gets copied 4 times on the If.
2020-07-09 Luke Kenneth Casso... ALU output stage, change logic slightly
2020-07-09 Luke Kenneth Casso... clarifying comments on setting xer_ov/so
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-06 Luke Kenneth Casso... remove alu unneeded op record data
2020-07-06 Luke Kenneth Casso... remove alu unneeded op record data
2020-07-06 Luke Kenneth Casso... remove alu unneeded op record data
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-06-11 Luke Kenneth Casso... read and write version of get_sim_xer_ca are different
2020-06-11 Luke Kenneth Casso... rename get_sim_cr_a to get_wr_sim_cr_a for now
2020-06-10 Luke Kenneth Casso... use sim-get helpers in ALU input fetch
2020-06-10 Luke Kenneth Casso... continue ALUHelpers check alu outputs code-morph
2020-06-10 Luke Kenneth Casso... code-morph ALU output test check phase
2020-06-10 Luke Kenneth Casso... code-munge test_pipe_caller for ALU,
2020-06-08 Luke Kenneth Casso... more verbose debug information tracking down SO/OV...
2020-06-08 Luke Kenneth Casso... set only the SO bit as sticky, not the OV flags as...
next