Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / branch / formal / proof_main_stage.py
2021-12-09 Jacob Lifshayadd parent_pspec everywhere
2021-12-09 Jacob Lifshayformat code
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2020-07-22 Luke Kenneth Casso... comments, add page spec numbers for branch ops into...
2020-07-22 Luke Kenneth Casso... fix branch main_stage proof, add ctr 32-bit, fix BCREG
2020-07-22 Luke Kenneth Casso... rework branch proof to use br_input_record
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-04 Luke Kenneth Casso... more updating spr1/spr2 to fast1/fast2
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-06-01 Luke Kenneth Casso... swap over SPR1/2 to fit with microwatt SPR conventions
2020-05-24 Michael NolanAssert that ctr is only written when needed
2020-05-24 Luke Kenneth Casso... comment and add links to branch formal proof
2020-05-22 Luke Kenneth Casso... test branch ctr ok flag
2020-05-22 Luke Kenneth Casso... cleaner way to test link register ok
2020-05-22 Luke Kenneth Casso... whitespace
2020-05-22 Michael NolanFix link handling in branch proof
2020-05-22 Luke Kenneth Casso... variable-name munging for branch formal
2020-05-22 Michael NolanAdd formal proof for branch unit, fix bug with bcreg
2020-05-18 Luke Kenneth Casso... mass-rename of modules to soc.fu.*
2020-05-18 Luke Kenneth Casso... rename pipe to fu