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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
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soc
/
fu
/
branch
/
formal
/
proof_main_stage.py
2021-12-09
Jacob Lifshay
add parent_pspec everywhere
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2021-12-09
Jacob Lifshay
format code
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2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
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2020-07-22
Luke Kenneth Casso...
comments, add page spec numbers for branch ops into...
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2020-07-22
Luke Kenneth Casso...
fix branch main_stage proof, add ctr 32-bit, fix BCREG
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2020-07-22
Luke Kenneth Casso...
rework branch proof to use br_input_record
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2020-07-12
Luke Kenneth Casso...
rename InternalOp to MicrOp
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-04
Luke Kenneth Casso...
more updating spr1/spr2 to fast1/fast2
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2020-06-04
Luke Kenneth Casso...
use copy of FHDLTestCase
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2020-06-01
Luke Kenneth Casso...
swap over SPR1/2 to fit with microwatt SPR conventions
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2020-05-24
Michael Nolan
Assert that ctr is only written when needed
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2020-05-24
Luke Kenneth Casso...
comment and add links to branch formal proof
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2020-05-22
Luke Kenneth Casso...
test branch ctr ok flag
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2020-05-22
Luke Kenneth Casso...
cleaner way to test link register ok
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2020-05-22
Luke Kenneth Casso...
whitespace
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2020-05-22
Michael Nolan
Fix link handling in branch proof
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2020-05-22
Luke Kenneth Casso...
variable-name munging for branch formal
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2020-05-22
Michael Nolan
Add formal proof for branch unit, fix bug with bcreg
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2020-05-18
Luke Kenneth Casso...
mass-rename of modules to soc.fu.*
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2020-05-18
Luke Kenneth Casso...
rename pipe to fu
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