move pc_i and svstate_i inside if self.run_hdl
[soc.git] / src / soc / fu / common_input_stage.py
2021-05-06 Luke Kenneth Casso... if zeroing is set, put zero into input or output as...
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... reorg of SO handling related to CR0
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB
2020-08-22 Luke Kenneth Casso... bug in andc and orc, complement was taking place on...
2020-08-17 Luke Kenneth Casso... turn SelectableInt less/greater into signed versions.
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-06-03 Luke Kenneth Casso... only select xer_xo if OE enabled
2020-06-01 Luke Kenneth Casso... remove zero/invert from ShiftRot Input Record
2020-05-27 Luke Kenneth Casso... remove XER.ca from logical Input Data - not needed
2020-05-22 Luke Kenneth Casso... split out Logical Input and Output stages to common...
2020-05-22 Luke Kenneth Casso... create common input pipe spec to avoid code-duplication