move pc_i and svstate_i inside if self.run_hdl
[soc.git] / src / soc / fu / compunits /
34 hours ago Luke Kenneth Casso... alter setup_tst_memory to take a test.mem rather than...
4 days ago Cesar StraussFix rel_o/go_i signal names
4 days ago Cesar StraussFix import
2021-09-08 Cesar StraussRemove default argument for dict.get()
2021-09-03 Luke Kenneth Casso... another batch of ready/valid i/o prefix-suffix swaps
2021-08-31 Luke Kenneth Casso... anooother valid_o to convert to o_valid
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2021-08-01 Jonathan Neuschäfersoc.simple.test: Rename setup_test_memory to avoid...
2021-05-04 Luke Kenneth Casso... add printout showing exception output from FUs
2021-05-04 Luke Kenneth Casso... more rename of exception_o to exc_o, add convenience...
2021-04-30 Luke Kenneth Casso... add a TestSRAM variant of LoadStore1, for being able...
2021-04-23 Luke Kenneth Casso... fix import error
2021-04-23 Luke Kenneth Casso... import from openpower.endian
2021-04-23 Luke Kenneth Casso... use openpower.test.common
2021-04-23 Luke Kenneth Casso... move more files to openpower-isa
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-04-20 Luke Kenneth Casso... add enable MMU option to issuer_verilog.py
2021-01-16 Tobias Platenmove microwatt_mmu bool variable to pspec
2021-01-15 Tobias Platenadd microwatt_mmu boolean variable to core and compunits
2021-01-10 Tobias Platenadd microwatt mmu config option to compunits.py
2020-12-06 Cesar StraussWhitespace
2020-12-06 Cesar StraussUpdate GTKWave documents to work with latest cxxsim
2020-12-05 Cesar StraussWrite a GTKWave document to investigate why the proof...
2020-12-05 Cesar StraussUse the DummyALU regspec and its corresponding OpSubset
2020-11-28 Cesar StraussFix signal names: go/rel -> go_i/rel_o
2020-10-12 Cole Poirierfix ModuleNotFound/Import errors found when running...
2020-10-06 Luke Kenneth Casso... skip Decode2ToOperand from PowerDecodeSubset
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-22 Luke Kenneth Casso... add MMU (commented out)
2020-09-15 Luke Kenneth Casso... instantiate MMU from AllFunctionUnits
2020-09-07 Luke Kenneth Casso... add pspec and opsubsetkls to CompUnits
2020-09-02 Luke Kenneth Casso... series of extensive modifications to fix long-standing...
2020-08-29 Luke Kenneth Casso... CR FXM becomes a full mask.
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... sorting out shift_rot to use new output stage data...
2020-08-26 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-26 Luke Kenneth Casso... investigating div fsm and simulator bug
2020-08-24 Luke Kenneth Casso... make it easier to select FSM/Pipe DIV unit
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-22 Luke Kenneth Casso... moved to div pipe temporarily in compunits
2020-08-14 Luke Kenneth Casso... fix test_compunit.py after moving decoder rdflags function
2020-08-14 Luke Kenneth Casso... sort out instruction stop/cancel when adding a new...
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-05 Luke Kenneth Casso... add div FSM as default for test_issuer in verilog and...
2020-08-04 Luke Kenneth Casso... msr and pc moved to "state" in PowerDecode2
2020-07-31 Luke Kenneth Casso... missed go_i/rel_o rename
2020-07-29 Luke Kenneth Casso... bit of a big change: add prefixes "cu_" to all CompUnit...
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-26 Luke Kenneth Casso... argh add yet another latch to detect when LD/ST has...
2020-07-26 Luke Kenneth Casso... sigh, issue with detection/waiting for LD/ST CompUnit
2020-07-26 Luke Kenneth Casso... convert LDST test to accumulator style
2020-07-26 Luke Kenneth Casso... convert Branch test to accumulator style
2020-07-26 Luke Kenneth Casso... convert SPR test to accumulator style
2020-07-26 Luke Kenneth Casso... convert TRAP test to accumulator style
2020-07-26 Luke Kenneth Casso... convert CR test to accumulator style
2020-07-26 Luke Kenneth Casso... convert shift_rot test to new base accumulator style
2020-07-26 Luke Kenneth Casso... convert logical test case to new base class accumulator...
2020-07-26 Luke Kenneth Casso... convert ALU to new accumulator style
2020-07-26 Luke Kenneth Casso... run subtest, indentation getting too large, move to...
2020-07-26 Luke Kenneth Casso... get div compunit test running (use new way to accumulat...
2020-07-25 Luke Kenneth Casso... add div compunit test
2020-07-25 Luke Kenneth Casso... wait until pipeline indicates that its output is valid...
2020-07-25 Luke Kenneth Casso... move reset of rdmaskn to after "busy"
2020-07-25 Luke Kenneth Casso... comment LDST FunctionUnit
2020-07-25 Luke Kenneth Casso... going on a bit of a "naming" spree, this for Jean-Paul...
2020-07-22 Jacob Lifshayworking on fsm
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-21 Luke Kenneth Casso... interesting bug in test_compunit.py when there are...
2020-07-21 Luke Kenneth Casso... move cia and msr to trap input record
2020-07-18 Luke Kenneth Casso... missing conversion of DIV to Div
2020-07-16 Luke Kenneth Casso... get shiftrot compunit working
2020-07-16 Luke Kenneth Casso... get branch compunit working (missing bigendian arg)
2020-07-16 Luke Kenneth Casso... get trap compunit test working, adding bigendian and msr
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... add bigendian flag
2020-07-11 Luke Kenneth Casso... add endian
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-10 Luke Kenneth Casso... re-add rc/oe back into LDST input record
2020-07-10 Luke Kenneth Casso... whew panic over, missed a bigendian argument in test_co...
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... add in SPR test cases into test_issuer.py
2020-07-06 Luke Kenneth Casso... add mul compunit
2020-07-06 Luke Kenneth Casso... adding mtspr tests
2020-07-06 Luke Kenneth Casso... sort out initialisation of TstL0CacheBuffer in ldst...
2020-07-05 Luke Kenneth Casso... check trap compunit output properly
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth Casso... sigh read and write xer detection, fix spr and trap...
2020-07-05 Luke Kenneth Casso... check spr1 in test spr compunit
2020-07-05 Luke Kenneth Casso... add first spr compunit test (not working yet)
2020-07-05 Luke Kenneth Casso... comment out SPR for now, needs SPR regfile
2020-07-05 Luke Kenneth Casso... add SPR compunit
2020-07-04 Luke Kenneth Casso... more updating spr1/spr2 to fast1/fast2
2020-07-04 Luke Kenneth Casso... oops initialise Function Unit class with idx
2020-07-04 Luke Kenneth Casso... add first cookie-cut test_trap_compunit.py
2020-07-02 Luke Kenneth Casso... allow flexible selection of the types of ALUs
2020-07-02 Luke Kenneth Casso... fix unit tests due to change in using pspec
2020-07-02 Luke Kenneth Casso... allow ALU names to propagate through from FU to CompUni...
2020-07-02 Luke Kenneth Casso... name function unit ALUs
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