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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / div / core_stages.py
2021-10-10 Luke Kenneth Casso... replace PartitionedSignal with SimdSignal blob | commitdiff | raw
2021-04-23 Luke Kenneth Casso... move over to from openpower imports blob | commitdiff | raw | diff to current
2020-07-17 Jacob Lifshayadd simulation-only division core using nmigen div... blob | commitdiff | raw | diff to current
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp blob | commitdiff | raw | diff to current
2020-07-10 Luke Kenneth Casso... code comments blob | commitdiff | raw | diff to current
2020-07-09 Luke Kenneth Casso... remove xer_ca from DIV pipeline (took a bit of messing... blob | commitdiff | raw | diff to current
2020-06-18 Jacob Lifshaydiv pipe completed except for tests blob | commitdiff | raw | diff to current
2020-06-18 Jacob Lifshayworking on adding rest of stage classes for div pipeline blob | commitdiff | raw | diff to current