Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / div / output_stage.py
2021-10-10 Luke Kenneth Casso... replace PartitionedSignal with SimdSignal
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2020-10-06 Jacob Lifshayadd workaround for nmigen bug #502
2020-07-25 Luke Kenneth Casso... remove old div overflow test, keep microwatt version
2020-07-25 Luke Kenneth Casso... comb += missing
2020-07-22 Jacob Lifshayworking on fsm
2020-07-17 Jacob Lifshayrename DIV->Div to be consistent
2020-07-17 Jacob Lifshayformat div code
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-10 Luke Kenneth Casso... do not set div result if overflow occurs
2020-07-10 Luke Kenneth Casso... add test7 div regression
2020-07-09 Luke Kenneth Casso... add regression test for div overflow case
2020-07-09 Luke Kenneth Casso... set xer_ov.ok = 1
2020-07-09 Luke Kenneth Casso... DIV overflow needs to be copied into both bits of XER.ov
2020-07-09 Luke Kenneth Casso... remove xer_ca from DIV pipeline (took a bit of messing...
2020-07-09 Luke Kenneth Casso... add new stages etc. to get multiply working without...
2020-06-30 Luke Kenneth Casso... code-morph on div pipeline
2020-06-18 Jacob Lifshayfinish code to calculate the 64-bit output of the div...
2020-06-18 Jacob Lifshayactually remove todo comment for manually checking...
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Jacob Lifshayfix bug and manually check div overflow code against...
2020-06-18 Jacob Lifshayworking on adding rest of stage classes for div pipeline