Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / div / pipeline.py
2022-05-01 Luke Kenneth Casso... split out front of div into separate stage, still too...
2022-04-30 Luke Kenneth Casso... add missing module
2022-04-30 Luke Kenneth Casso... split off CR0/XER production in DIV Function Unit into...
2020-07-22 Jacob Lifshayworking on fsm
2020-07-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-18 Jacob Lifshayadd div fsm core (`DivState*`) with tests
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Jacob Lifshaystart adding FSMDivCore*
2020-07-17 Jacob Lifshayrename DIV->Div to be consistent
2020-07-17 Jacob Lifshayformat div code
2020-07-10 Luke Kenneth Casso... add debugging chain for #425
2020-07-09 Luke Kenneth Casso... remove xer_ca from DIV pipeline (took a bit of messing...
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-04 Luke Kenneth Casso... reduce steps per stage to 8
2020-07-02 Luke Kenneth Casso... increase combinatorial stages to 8
2020-06-29 Luke Kenneth Casso... sort out syntax errors in div
2020-06-19 Luke Kenneth Casso... whitespace update
2020-06-18 Jacob Lifshaydiv pipe completed except for tests
2020-05-22 Luke Kenneth Casso... cookie-cut start on div pipe