Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / div / setup_stage.py
2022-02-27 Luke Kenneth Casso... start on converting MUL and DIV pipelines to XLEN
2021-10-10 Luke Kenneth Casso... replace PartitionedSignal with SimdSignal
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2020-07-17 Jacob Lifshayrename DIV->Div to be consistent
2020-07-17 Jacob Lifshayformat div code
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-09 Luke Kenneth Casso... remove xer_ca from DIV pipeline (took a bit of messing...
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-06 Luke Kenneth Casso... first cut at mul test pipeline
2020-06-30 Luke Kenneth Casso... code-morph on div pipeline
2020-06-29 Luke Kenneth Casso... sort out syntax errors in div
2020-06-18 Jacob Lifshayworking on adding rest of stage classes for div pipeline
2020-06-10 Jacob Lifshaycreate div pipe setup stage