skip ilang data in branch test_pipe_caller.py
[soc.git] / src / soc / fu / ldst / loadstore.py
5 days ago Luke Kenneth Casso... raise interrupt on misaligned atomic LDST
5 days ago Luke Kenneth Casso... pass over store_done correctly from dcache over PortInt...
5 days ago Luke Kenneth Casso... add CR0 to LDSTCompUnit, for reporting if LR/SC store...
6 days ago Luke Kenneth Casso... pass over atomic signals to dcache from loadstore.
6 days ago Luke Kenneth Casso... pass atomic reserve through from PortInterface to DCache
9 days ago Luke Kenneth Casso... fix issue with priv_mode not being passed correctly...
11 days ago Luke Kenneth Casso... LoadStore1 priv_mode was not being correctly picked...
13 days ago Luke Kenneth Casso... fix MMU lookup after 2nd request (misaligned) by also...
13 days ago Luke Kenneth Casso... do not clear out ldst request after TLB entry is added
13 days ago Luke Kenneth Casso... add a second LD request to dcache which is merged with...
13 days ago Luke Kenneth Casso... start adding in mis-aligned LD/ST support into LoadStore1
2022-01-06 Luke Kenneth Casso... add SECOND_REQ state to loadstore.py, not yet implemented
2022-01-03 Luke Kenneth Casso... adding an extra option to issuer_verilog.py to be able...
2021-12-28 Luke Kenneth Casso... add misaligned mmu.bin test 5 notes: currently LoadStor...
2021-12-26 Luke Kenneth Casso... rename addr to raddr in LoadStore1 to avoid conflict...
2021-12-22 Luke Kenneth Casso... when setting DSISR in LoadStore1 use correct load bit...
2021-12-22 Luke Kenneth Casso... remove unneeded state in LoadStore1
2021-12-22 Luke Kenneth Casso... clear instruction fault on exception WAIT_MMU ACK in...
2021-12-22 Luke Kenneth Casso... clear out instr_fault when exception is thrown
2021-12-22 Luke Kenneth Casso... clear instruction fault on idle/valid in Loadstore1
2021-12-14 Luke Kenneth Casso... get OP_FETCH_FAILED to respond/return an exception...
2021-12-13 Luke Kenneth Casso... convert LoadStore1 to new msr.pr/dr/sf
2021-12-11 Luke Kenneth Casso... connect up I-Cache to FetchUnitInterface
2021-12-08 Luke Kenneth Casso... make LoadStore1 intsr_fault a "captured flag" - strictl...
2021-12-08 Luke Kenneth Casso... add instr_fault to LoadStore1 FSM
2021-12-07 Luke Kenneth Casso... set separate "iside" signal in LoadStore1 to not confuse it
2021-12-07 Luke Kenneth Casso... add in I-Cache into LoadStore1 - presently unused ...
2021-12-05 Luke Kenneth Casso... wishbone bus convert on dcache
2021-12-04 Luke Kenneth Casso... put DSISR and DAR publicly accessible in LoadStore1
2021-12-04 Luke Kenneth Casso... whoops fix up exception happened if alignment triggers...
2021-12-04 Luke Kenneth Casso... fixing DAR updating from exceptions
2021-12-04 Luke Kenneth Casso... MMU lookup DSISR load bit inverted in LoadStore1
2021-12-04 Luke Kenneth Casso... store DAR in LoadStore1
2021-12-04 Luke Kenneth Casso... not busy if excrption occurs on MMU_LOOKUP in loadstore.py
2021-12-04 Luke Kenneth Casso... add means to update dsisr from MMU FSM. TODO: add a...
2021-12-03 Luke Kenneth Casso... priv_mode/virt_mode are set in the request, which is...
2021-12-03 Luke Kenneth Casso... in loadstore.py set align_intr from request which comes...
2021-12-03 Luke Kenneth Casso... driver conflict on priv_mode and virt_mode, do not...
2021-12-03 Luke Kenneth Casso... in loadstore.py, when an exception is done or if the FSM
2021-11-30 Tobias Platenreturn correct data from microwatt
2021-11-30 Tobias Platenloadstore: add done_delay
2021-11-25 Tobias Platenremove unuses dsisr signal
2021-11-25 Tobias Platenreset state to idle on exception
2021-11-16 Tobias Platenloadstore1 now reports exception reason
2021-11-15 Tobias Platenreport dar on exception + test case
2021-11-03 Tobias Platenloadstore.py: add Display statement on SPR change
2021-10-30 Tobias Platenloadstore.py: add debug output for dcbz
2021-10-08 Tobias Platenan extra dcbz parameter in all six places
2021-10-08 Luke Kenneth Casso... commented-out and disabled the set_dcbz_addr function...
2021-10-08 Tobias Platendcbz symbol rename
2021-10-08 Tobias Platenloadstore.py: add function set_dcbz_addr
2021-10-03 Tobias Platenan extra dcbz parameter in all six places
2021-10-02 Luke Kenneth Casso... commented-out and disabled the set_dcbz_addr function...
2021-10-02 Tobias Platendcbz symbol rename
2021-10-02 Tobias Platenloadstore.py: add function set_dcbz_addr
2021-07-23 Tobias Platenldst: cleanup debug outputs
2021-07-14 Tobias Platenadd more debug outputs, pass dcbz to loadstore/dcache
2021-07-11 Tobias Platenpass self.pi.is_dcbz to request
2021-06-18 Tobias Platensrc/soc/fu/ldst/loadstore.py: keep data for the whole...
2021-05-14 Luke Kenneth Casso... clear out request data on return to idle
2021-05-14 Luke Kenneth Casso... sort out LoadStore1 misalignment FSM, also required...
2021-05-12 Luke Kenneth Casso... set m_out.load from ldst_r(egister) in LoadStore1
2021-05-12 Luke Kenneth Casso... experimentation with MMU-enabled LoadStore1 through...
2021-05-12 Luke Kenneth Casso... add debug info, update comments, disable dcache in...
2021-05-12 Luke Kenneth Casso... start doing virtual memory queries via PortInterface...
2021-05-11 Luke Kenneth Casso... pass through MSR.PR through PortInterface, into LoadStore1
2021-05-11 Luke Kenneth Casso... comment tidyup
2021-05-11 Luke Kenneth Casso... must also pass through instruction fault exception...
2021-05-11 Luke Kenneth Casso... tidyup comments and remove LoadStore COMPLETE state
2021-05-11 Luke Kenneth Casso... cleanup on exception setting
2021-05-11 Luke Kenneth Casso... rename LoadStore1 data structures back to microwatt...
2021-05-10 Luke Kenneth Casso... add block for MMU activation to LoadStore1
2021-05-10 Luke Kenneth Casso... move LoadStore1 d_validblip setting, and get MMU_LOOKUP...
2021-05-10 Tobias Platenstyle-wise: use ~self.instr_fault not self.instr_fault==0
2021-05-10 Tobias PlatenLoadStore1: add rules for MMU_LOOKUP
2021-05-09 Luke Kenneth Casso... add comments on translation of MMU_LOOKUP
2021-05-09 Luke Kenneth Casso... install MMU_LOOKUP vhdl to be translated to nmigen
2021-05-09 Luke Kenneth Casso... move (unused) ACK_WAIT code into FSM
2021-05-09 Luke Kenneth Casso... add comments in LoadStore1
2021-05-09 Luke Kenneth Casso... remove invalid setting of d_in.valid from self.mmureq
2021-05-09 Luke Kenneth Casso... no SECOND_REQ
2021-05-09 Luke Kenneth Casso... remove SECOND_REQ
2021-05-09 Tobias Platensrc/soc/fu/ldst/loadstore.py drive output d_in.valid
2021-05-09 Tobias Platenmove skeleton to elaborate
2021-05-09 Tobias Platensrc/soc/fu/ldst/loadstore.py: add skeleton for fsm
2021-05-09 Luke Kenneth Casso... update code-comments
2021-05-09 Luke Kenneth Casso... add in alignment exception capture/reporting in LoadStore1
2021-05-09 Luke Kenneth Casso... add misalign flag to PortInterfaceBase
2021-05-08 Luke Kenneth Casso... LoadStore1 tidyup
2021-05-08 Luke Kenneth Casso... transferring more over to LoadStore FSM
2021-05-08 Luke Kenneth Casso... start putting state info into LoadStore1, slowly puttin...
2021-05-08 Luke Kenneth Casso... add LoadStore State enum
2021-05-07 Luke Kenneth Casso... start setting DSISR bits but commented out
2021-05-07 Luke Kenneth Casso... move LoadStore1 class to soc.fu.ldst.loadstore