rename invert_a to invert_in because logical inverts RB
[soc.git] / src / soc / fu / logical / logical_input_record.py
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB
2020-07-14 Luke Kenneth Casso... reduce code size by using CompOpSubsetBase for ALU...
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... remove unneeded record field from logical_input_record
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-05-31 Luke Kenneth Casso... add logical compunit test
2020-05-21 Luke Kenneth Casso... add fu logical_input_record.py