remove unneeded imports
[soc.git] / src / soc / fu / logical / pipe_data.py
2020-06-06 Luke Kenneth Casso... remove unneeded imports
2020-06-06 Luke Kenneth Casso... noticed the regular pattern in all pipe_data.py (regspecs).
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... remove rdflags in pipe_data.py (redundant)
2020-06-02 Luke Kenneth Casso... rename regspecs to give a consistent naming scheme
2020-06-01 Luke Kenneth Casso... okaaay add a "rdflags" function which obtains the yes...
2020-05-31 Luke Kenneth Casso... add logical compunit test
2020-05-27 Luke Kenneth Casso... LogicalOutputData does not need XER.so
2020-05-27 Luke Kenneth Casso... remove XER.ca from logical Input Data - not needed
2020-05-24 Luke Kenneth Casso... output registers need to be Data type (consistently)
2020-05-22 Luke Kenneth Casso... split out Logical Input and Output stages to common...
2020-05-21 Luke Kenneth Casso... move Logical over to use CompLogicalOpSubset
2020-05-21 Luke Kenneth Casso... move common functionality between PipeSpecs to soc...
2020-05-21 Luke Kenneth Casso... move FU IntegerData to directory below
2020-05-21 Luke Kenneth Casso... convert to individual PipeSpecs for each pipeline
2020-05-20 Luke Kenneth Casso... add register specs to pipeline in/out so that they...
2020-05-20 Luke Kenneth Casso... normalise XER regs carry/32 and SO
2020-05-19 Luke Kenneth Casso... rename ALUPipeData to LogicalPipeData
2020-05-18 Luke Kenneth Casso... mass-rename of modules to soc.fu.*
2020-05-18 Luke Kenneth Casso... rename pipe to fu