Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / logical / test /
2023-09-11 Jacob Lifshayset 'soc' filter to filter out v3.1 insns
2022-02-27 Luke Kenneth Casso... fix up Logical pipeline to produce HDL with XLEN=32
2021-12-09 Jacob Lifshayadd parent_pspec everywhere
2021-12-09 Jacob Lifshayformat code
2021-08-30 Luke Kenneth Casso... missed valid/ready_i/o to o/i_ conversion
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-04-23 Luke Kenneth Casso... move logical tests to openpower.test
2021-04-23 Luke Kenneth Casso... import from openpower.endian
2021-04-23 Luke Kenneth Casso... use openpower.test.common
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-01-04 Tobias Platentest_countzero.py: rename output files
2020-10-06 Luke Kenneth Casso... use pdecode2.do not pdecode2.e in test_pipe_caller...
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... reorg of SO handling related to CR0
2020-08-26 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-26 Luke Kenneth Casso... use sub-test in logical test_pipe_caller
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-22 Luke Kenneth Casso... add eqv to logical unit test
2020-08-22 Luke Kenneth Casso... add nor and nand to unit test
2020-08-22 Luke Kenneth Casso... add andc and orc tests, failing because RB needs invers...
2020-08-14 Luke Kenneth Casso... divide logical pipe into 2 (simple phase last)
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-26 Luke Kenneth Casso... convert logical test case to new base class accumulator...
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-06-11 Luke Kenneth Casso... rename get_sim_cr_a to get_wr_sim_cr_a for now
2020-06-10 Luke Kenneth Casso... use ALUHelpers in output stage of test_pipe_caller
2020-06-10 Luke Kenneth Casso... move to common ALUHelpers for Logical test_pipe_caller.py
2020-06-07 Luke Kenneth Casso... add missing args to ISA
2020-06-04 Luke Kenneth Casso... use common TestCase class in logical
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... move obtaining simulator data into common function...
2020-06-01 Luke Kenneth Casso... remove use of reg3 in logical pipeline: CSV files moved...
2020-05-27 Luke Kenneth Casso... remove XER.ca from logical Input Data - not needed
2020-05-24 Michael NolanFix test_pipe_caller to conform to new Data() interface...
2020-05-22 Luke Kenneth Casso... split out Logical Input and Output stages to common...
2020-05-21 Luke Kenneth Casso... move common functionality between PipeSpecs to soc...
2020-05-21 Luke Kenneth Casso... move FU IntegerData to directory below
2020-05-21 Luke Kenneth Casso... convert to individual PipeSpecs for each pipeline
2020-05-20 Michael NolanMake test for bpermd exercise the module a bit more
2020-05-20 colepoirierAdded OP_BPERMD to fu/logical pipeline, with test
2020-05-20 Luke Kenneth Casso... normalise XER regs carry/32 and SO
2020-05-20 Michael NolanAdd test for edge cases that were previously buggy
2020-05-20 Luke Kenneth Casso... convert Logical to use new XER use of Data()
2020-05-19 Michael NolanImplement 32 bit cntlz and cnttz
2020-05-19 Michael NolanActually implement cntlzd
2020-05-18 Luke Kenneth Casso... move countzero to fu/logical
2020-05-18 Luke Kenneth Casso... mass-rename of modules to soc.fu.*
2020-05-18 Luke Kenneth Casso... rename pipe to fu