move pc_i and svstate_i inside if self.run_hdl
[soc.git] / src / soc / fu / logical /
2021-08-30 Luke Kenneth Casso... missed valid/ready_i/o to o/i_ conversion
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-06-10 Luke Kenneth Casso... whoops Popcount datalen too big (wasted bits). reduce
2021-05-04 Luke Kenneth Casso... rename IntegerData to FUBaseData
2021-04-23 Luke Kenneth Casso... move logical tests to openpower.test
2021-04-23 Luke Kenneth Casso... import from openpower.endian
2021-04-23 Luke Kenneth Casso... use openpower.test.common
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-01-04 Tobias Platentest_countzero.py: rename output files
2020-10-06 Luke Kenneth Casso... use pdecode2.do not pdecode2.e in test_pipe_caller...
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-07 Luke Kenneth Casso... bit of a big reorg of data structures
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... reorg of SO handling related to CR0
2020-08-26 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-26 Luke Kenneth Casso... use sub-test in logical test_pipe_caller
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-23 Michael NolanAdd copyright to files in fu/ that I was the primary...
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB
2020-08-22 Luke Kenneth Casso... add eqv to logical unit test
2020-08-22 Luke Kenneth Casso... add nor and nand to unit test
2020-08-22 Luke Kenneth Casso... bug in andc and orc, complement was taking place on...
2020-08-22 Luke Kenneth Casso... add andc and orc tests, failing because RB needs invers...
2020-08-14 Luke Kenneth Casso... divide logical pipe into 2 (simple phase last)
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-26 Luke Kenneth Casso... convert logical test case to new base class accumulator...
2020-07-25 Luke Kenneth Casso... add spec page numbers to logical ops
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-14 Luke Kenneth Casso... reduce code size by using CompOpSubsetBase for ALU...
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... remove unneeded record field from logical_input_record
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-06-16 Luke Kenneth Casso... update popcount docstring
2020-06-11 Luke Kenneth Casso... rename get_sim_cr_a to get_wr_sim_cr_a for now
2020-06-10 Luke Kenneth Casso... use ALUHelpers in output stage of test_pipe_caller
2020-06-10 Luke Kenneth Casso... move to common ALUHelpers for Logical test_pipe_caller.py
2020-06-07 Luke Kenneth Casso... add missing args to ISA
2020-06-06 Luke Kenneth Casso... remove unneeded imports
2020-06-06 Luke Kenneth Casso... noticed the regular pattern in all pipe_data.py (regspecs).
2020-06-04 Luke Kenneth Casso... use common TestCase class in logical
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... remove rdflags in pipe_data.py (redundant)
2020-06-03 Luke Kenneth Casso... move obtaining simulator data into common function...
2020-06-02 Luke Kenneth Casso... rename regspecs to give a consistent naming scheme
2020-06-01 Luke Kenneth Casso... okaaay add a "rdflags" function which obtains the yes...
2020-06-01 Luke Kenneth Casso... remove use of reg3 in logical pipeline: CSV files moved...
2020-05-31 Luke Kenneth Casso... add logical compunit test
2020-05-29 Luke Kenneth Casso... module comments for popcount
2020-05-29 Luke Kenneth Casso... comments on popcount
2020-05-28 Luke Kenneth Casso... move simple_popcount out of class (does not use any...
2020-05-27 Luke Kenneth Casso... LogicalOutputData does not need XER.so
2020-05-27 Luke Kenneth Casso... remove XER.ca from logical Input Data - not needed
2020-05-27 Luke Kenneth Casso... cleanup logical main proof
2020-05-24 Luke Kenneth Casso... add OP_CMPB formal proof
2020-05-24 Luke Kenneth Casso... split out Popcount into separate module: visually it...
2020-05-24 Luke Kenneth Casso... add copy of bpermd proof to logical formal proof (not...
2020-05-24 Luke Kenneth Casso... track down overwrite of variable b
2020-05-24 Michael NolanFix proof of bpermd module
2020-05-24 Michael NolanFix bpermd and make tests pass
2020-05-24 Michael NolanFix test_pipe_caller to conform to new Data() interface...
2020-05-24 Luke Kenneth Casso... convert logical to output Data on int reg
2020-05-24 Luke Kenneth Casso... output registers need to be Data type (consistently)
2020-05-23 Luke Kenneth Casso... add input / output stage missing modules
2020-05-22 Luke Kenneth Casso... cleanup logical pipe formal proof
2020-05-22 Luke Kenneth Casso... split out Logical Input and Output stages to common...
2020-05-22 Luke Kenneth Casso... soc.fu.logical.input_stage no different from ALU: delete
2020-05-22 Luke Kenneth Casso... comment tidyup
2020-05-21 Luke Kenneth Casso... add fu logical_input_record.py
2020-05-21 Luke Kenneth Casso... move Logical over to use CompLogicalOpSubset
2020-05-21 Luke Kenneth Casso... move common functionality between PipeSpecs to soc...
2020-05-21 Luke Kenneth Casso... move FU IntegerData to directory below
2020-05-21 Luke Kenneth Casso... convert to individual PipeSpecs for each pipeline
2020-05-20 Michael NolanMake test for bpermd exercise the module a bit more
2020-05-20 colepoirierAdded OP_BPERMD to fu/logical pipeline, with test
2020-05-20 Luke Kenneth Casso... add register specs to pipeline in/out so that they...
2020-05-20 Luke Kenneth Casso... formal proof rename on XER flags
2020-05-20 Luke Kenneth Casso... normalise XER regs carry/32 and SO
2020-05-20 Michael NolanAdd proof for OP_CNTZ
2020-05-20 Luke Kenneth Casso... add cross-reference to bugtracker and wiki
2020-05-20 Michael NolanAdd test for edge cases that were previously buggy
2020-05-20 Michael NolanDelete assume left over from testing
2020-05-20 Michael NolanAdd proof for OP_PRTY
2020-05-20 Michael NolanFormally verify OP_POPCNT
2020-05-20 Michael NolanFix bug with popcntd
2020-05-20 Luke Kenneth Casso... convert Logical to use new XER use of Data()
2020-05-20 Luke Kenneth Casso... whoops changed name of ALUInputData to LogicalInputData
2020-05-19 colepoirierRenamed bperm files in fu/logical and fu/logical formal...
2020-05-19 Luke Kenneth Casso... rename ALUPipeData to LogicalPipeData
2020-05-19 Luke Kenneth Casso... annoying syntax error
2020-05-19 Luke Kenneth Casso... code-shuffle on OP_CNTZ
2020-05-19 Michael NolanImplement 32 bit cntlz and cnttz
2020-05-19 Michael NolanActually implement cntlzd
2020-05-19 colepoirierAdded luke's suggested code to cover all 3 assertions...
2020-05-18 colepoirierAdded 2nd of 3 assertions for proof_bperm.py, currently...
2020-05-18 Luke Kenneth Casso... move countzero to fu/logical
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