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connect wishbone bus to test memory
[soc.git]
/
src
/
soc
/
fu
/
mmu
/
fsm.py
2021-01-19
Tobias Platen
connect wishbone bus to test memory
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2021-01-18
Tobias Platen
fu/mmu/fsm.py: connect valid and load signals
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2021-01-17
Tobias Platen
add test memory for simulation
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2021-01-16
Tobias Platen
clean up test case for tlbie and dcbz
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2021-01-06
Tobias Platen
fu/mmu/fsm.py: mfspr!=mtspr
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2020-11-16
Tobias Platen
add class LoadStore1(PortInterfaceBase)
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2020-11-07
Tobias Platen
fixed a bug in src/soc/fu/mmu/fsm.py
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2020-10-08
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-10-08
Luke Kenneth Casso...
add incoming PortInterface to be connected to LoadStore...
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2020-09-15
Luke Kenneth Casso...
instantiate MMU from AllFunctionUnits
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2020-09-15
Luke Kenneth Casso...
add edge-triggering to dcache/mmu "valid"
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2020-09-15
Luke Kenneth Casso...
add OP_MFSPR to mmu
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2020-09-15
Luke Kenneth Casso...
use convenience vars
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2020-09-15
Luke Kenneth Casso...
add OP_TLBIE to mmu fsm
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2020-09-15
Luke Kenneth Casso...
add OP_DCBZ to mmu fsm, needs RA to be added to MMU...
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2020-09-15
Luke Kenneth Casso...
add MMU MTSPR connection into FSM
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2020-09-15
Luke Kenneth Casso...
add in MMU and DCache into MMU FSM
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2020-09-15
Luke Kenneth Casso...
add mmu fsm
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