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connect wishbone bus to test memory
[soc.git] / src / soc / fu / mmu / fsm.py
2021-01-19 Tobias Platenconnect wishbone bus to test memory blob | commitdiff | raw
2021-01-18 Tobias Platenfu/mmu/fsm.py: connect valid and load signals blob | commitdiff | raw | diff to current
2021-01-17 Tobias Platenadd test memory for simulation blob | commitdiff | raw | diff to current
2021-01-16 Tobias Platenclean up test case for tlbie and dcbz blob | commitdiff | raw | diff to current
2021-01-06 Tobias Platenfu/mmu/fsm.py: mfspr!=mtspr blob | commitdiff | raw | diff to current
2020-11-16 Tobias Platenadd class LoadStore1(PortInterfaceBase) blob | commitdiff | raw | diff to current
2020-11-07 Tobias Platenfixed a bug in src/soc/fu/mmu/fsm.py blob | commitdiff | raw | diff to current
2020-10-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... blob | commitdiff | raw | diff to current
2020-10-08 Luke Kenneth Casso... add incoming PortInterface to be connected to LoadStore... blob | commitdiff | raw | diff to current
2020-09-15 Luke Kenneth Casso... instantiate MMU from AllFunctionUnits blob | commitdiff | raw | diff to current
2020-09-15 Luke Kenneth Casso... add edge-triggering to dcache/mmu "valid" blob | commitdiff | raw | diff to current
2020-09-15 Luke Kenneth Casso... add OP_MFSPR to mmu blob | commitdiff | raw | diff to current
2020-09-15 Luke Kenneth Casso... use convenience vars blob | commitdiff | raw | diff to current
2020-09-15 Luke Kenneth Casso... add OP_TLBIE to mmu fsm blob | commitdiff | raw | diff to current
2020-09-15 Luke Kenneth Casso... add OP_DCBZ to mmu fsm, needs RA to be added to MMU... blob | commitdiff | raw | diff to current
2020-09-15 Luke Kenneth Casso... add MMU MTSPR connection into FSM blob | commitdiff | raw | diff to current
2020-09-15 Luke Kenneth Casso... add in MMU and DCache into MMU FSM blob | commitdiff | raw | diff to current
2020-09-15 Luke Kenneth Casso... add mmu fsm blob | commitdiff | raw | diff to current