skip ilang data in branch test_pipe_caller.py
[soc.git] / src / soc / fu / mmu / fsm.py
9 days ago Luke Kenneth Casso... fix issue with priv_mode not being passed correctly...
10 days ago Luke Kenneth Casso... LoadStore1 priv_mode was not being correctly picked...
2021-12-30 Luke Kenneth Casso... rename nia to cia in MMU input record and mmu FSM
2021-12-18 Luke Kenneth Casso... forgot to connect up I-Cache to MMU
2021-12-14 Luke Kenneth Casso... get OP_FETCH_FAILED to respond/return an exception...
2021-12-14 Luke Kenneth Casso... MMU LOOKUP for fetch failed, priv mode is inversion...
2021-12-14 Luke Kenneth Casso... link MSR.PR into MMU FSM OP_FETCH_FAILED
2021-12-12 Luke Kenneth Casso... delay MMU LOOKUP done by one clock so that the exceptio...
2021-12-12 Luke Kenneth Casso... bring MMU exception out where AllFunctionUnits (and...
2021-12-12 Luke Kenneth Casso... bring exception out from MMU FSM, correct "done"
2021-12-09 Luke Kenneth Casso... add I-Cache to FSM local variables
2021-12-08 Luke Kenneth Casso... add OP_FETCH_FAILED to MMU Function Unit
2021-12-05 Luke Kenneth Casso... code-comments
2021-12-05 Luke Kenneth Casso... wishbone bus convert on dcache
2021-12-04 Luke Kenneth Casso... sigh in MMU FSM use direct access to ldst.dar/dsisr...
2021-12-04 Luke Kenneth Casso... add means to update dsisr from MMU FSM. TODO: add a...
2021-12-03 Luke Kenneth Casso... priv_mode/virt_mode are set in the request, which is...
2021-12-03 Luke Kenneth Casso... comment out dsisr and dar in mmu FSM for now
2021-11-10 Luke Kenneth Casso... whitespace
2021-11-08 Tobias Platenmmu unit test working again
2021-11-06 Tobias Platenupdate test_issuer_mmu.py testcase, add needed debug...
2021-11-04 Luke Kenneth Casso... fix missing naming ready_i -> i_ready
2021-11-03 Tobias Platencleanup fsm
2021-11-03 Tobias Platenadd first tlbie test case
2021-11-02 Tobias Platenmmu fsm: symbols have been renamed
2021-11-01 Tobias Platenhack: resolve DriverConflict in src/soc/fu/mmu/fsm.py
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2021-05-11 Luke Kenneth Casso... whoops names changed in MMU FSM
2021-05-09 Luke Kenneth Casso... add MMU bugtracker link
2021-05-09 Luke Kenneth Casso... preference is to create a temp variable for comb and...
2021-05-08 Luke Kenneth Casso... add bugreport link to mmu
2021-05-07 Tobias Platenfix 'sync' referenced before assignment in src/soc...
2021-05-07 Luke Kenneth Casso... update comments and docstrings
2021-05-07 Luke Kenneth Casso... whoops, import error
2021-05-07 Luke Kenneth Casso... move LoadStore1 class to soc.fu.ldst.loadstore
2021-05-07 Luke Kenneth Casso... move dsisr and dar into LoadStore1
2021-05-05 Tobias Platenfix bug in mmu/fsm.py
2021-05-04 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-05-04 Tobias Platenimplement MFSPR the same way as fu/spr/main_stage.py
2021-05-04 Tobias Platenupate dsisr and dar using sync
2021-05-04 Luke Kenneth Casso... more rename of exception_o to exc_o, add convenience...
2021-05-04 Luke Kenneth Casso... comment out nc (nocache), it seems to actually work
2021-05-03 Luke Kenneth Casso... MMU: get store to activate only when data is available...
2021-05-03 Luke Kenneth Casso... disable the cache for now, whilst testing read/write...
2021-05-02 Luke Kenneth Casso... use Const to define bit-length when comparing top nibbl...
2021-05-02 Luke Kenneth Casso... mmu FSM store in dcache: only put data onto d_in on...
2021-05-02 Luke Kenneth Casso... return d_out.valid instead of always "ok" in MMU FSM
2021-05-02 Luke Kenneth Casso... HACK WARNING: disable d-cache on hard-coded address...
2021-05-01 Luke Kenneth Casso... store data in microwatt dcache goes in one cycle AFTER...
2021-05-01 Luke Kenneth Casso... only do dcache lookup for now
2021-04-30 Luke Kenneth Casso... comments on dcache-to-mmu link
2021-04-30 Luke Kenneth Casso... add a TestSRAM variant of LoadStore1, for being able...
2021-04-30 Luke Kenneth Casso... hook up dcache wb_in/out to PortInterfaceBase Wishbone...
2021-04-30 Luke Kenneth Casso... set up LoadStore1 in ConfigMemoryPortInterface and...
2021-04-29 Luke Kenneth Casso... comment out adding mmu and dcache to pspec in MMU FSM
2021-04-29 Luke Kenneth Casso... move dcache into Loadstore1
2021-04-27 Luke Kenneth Casso... return read data out from Loadstore1 only when valid
2021-04-26 Luke Kenneth Casso... hook up MSR into MMU (TODO, use a lot less bits)
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size
2021-03-02 Luke Kenneth Casso... operating correctly, not directing MMU SPRs to SPR...
2021-03-02 Luke Kenneth Casso... must always set ok for writing out data otherwise it...
2021-02-18 Tobias Platenmmu: remove TestMemory
2021-02-16 Tobias Platenmmureq handling
2021-02-16 Tobias Platendcache error handling
2021-02-05 Tobias Platenfix hanging simulation
2021-02-04 Tobias Platensrc/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
2021-01-19 Tobias Platenconnect LDSTException to MMU and DCache
2021-01-19 Tobias Platenconnect wishbone bus to test memory
2021-01-18 Tobias Platenfu/mmu/fsm.py: connect valid and load signals
2021-01-17 Tobias Platenadd test memory for simulation
2021-01-16 Tobias Platenclean up test case for tlbie and dcbz
2021-01-06 Tobias Platenfu/mmu/fsm.py: mfspr!=mtspr
2020-11-16 Tobias Platenadd class LoadStore1(PortInterfaceBase)
2020-11-07 Tobias Platenfixed a bug in src/soc/fu/mmu/fsm.py
2020-10-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-10-08 Luke Kenneth Casso... add incoming PortInterface to be connected to LoadStore...
2020-09-15 Luke Kenneth Casso... instantiate MMU from AllFunctionUnits
2020-09-15 Luke Kenneth Casso... add edge-triggering to dcache/mmu "valid"
2020-09-15 Luke Kenneth Casso... add OP_MFSPR to mmu
2020-09-15 Luke Kenneth Casso... use convenience vars
2020-09-15 Luke Kenneth Casso... add OP_TLBIE to mmu fsm
2020-09-15 Luke Kenneth Casso... add OP_DCBZ to mmu fsm, needs RA to be added to MMU...
2020-09-15 Luke Kenneth Casso... add MMU MTSPR connection into FSM
2020-09-15 Luke Kenneth Casso... add in MMU and DCache into MMU FSM
2020-09-15 Luke Kenneth Casso... add mmu fsm