move pc_i and svstate_i inside if self.run_hdl
[soc.git] / src / soc / fu / mmu /
2021-09-03 Luke Kenneth Casso... another batch of ready/valid i/o prefix-suffix swaps
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2021-05-11 Luke Kenneth Casso... whoops names changed in MMU FSM
2021-05-09 Luke Kenneth Casso... add MMU bugtracker link
2021-05-09 Luke Kenneth Casso... preference is to create a temp variable for comb and...
2021-05-08 Luke Kenneth Casso... add bugreport link to mmu
2021-05-07 Tobias Platenfix 'sync' referenced before assignment in src/soc...
2021-05-07 Luke Kenneth Casso... update comments and docstrings
2021-05-07 Luke Kenneth Casso... whoops, import error
2021-05-07 Luke Kenneth Casso... move LoadStore1 class to soc.fu.ldst.loadstore
2021-05-07 Luke Kenneth Casso... move dsisr and dar into LoadStore1
2021-05-05 Tobias Platenfix bug in mmu/fsm.py
2021-05-04 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-05-04 Tobias Platenimplement MFSPR the same way as fu/spr/main_stage.py
2021-05-04 Tobias Platenupate dsisr and dar using sync
2021-05-04 Luke Kenneth Casso... more rename of exception_o to exc_o, add convenience...
2021-05-04 Luke Kenneth Casso... rename IntegerData to FUBaseData
2021-05-04 Luke Kenneth Casso... comment out nc (nocache), it seems to actually work
2021-05-03 Luke Kenneth Casso... MMU: get store to activate only when data is available...
2021-05-03 Luke Kenneth Casso... disable the cache for now, whilst testing read/write...
2021-05-02 Luke Kenneth Casso... use Const to define bit-length when comparing top nibbl...
2021-05-02 Luke Kenneth Casso... mmu FSM store in dcache: only put data onto d_in on...
2021-05-02 Luke Kenneth Casso... return d_out.valid instead of always "ok" in MMU FSM
2021-05-02 Luke Kenneth Casso... HACK WARNING: disable d-cache on hard-coded address...
2021-05-01 Luke Kenneth Casso... store data in microwatt dcache goes in one cycle AFTER...
2021-05-01 Luke Kenneth Casso... only do dcache lookup for now
2021-04-30 Luke Kenneth Casso... debug and stop on mmu test_pipe_caller.py
2021-04-30 Luke Kenneth Casso... comments on dcache-to-mmu link
2021-04-30 Luke Kenneth Casso... add a TestSRAM variant of LoadStore1, for being able...
2021-04-30 Luke Kenneth Casso... hook up dcache wb_in/out to PortInterfaceBase Wishbone...
2021-04-30 Luke Kenneth Casso... set up LoadStore1 in ConfigMemoryPortInterface and...
2021-04-29 Luke Kenneth Casso... comment out adding mmu and dcache to pspec in MMU FSM
2021-04-29 Luke Kenneth Casso... move dcache into Loadstore1
2021-04-27 Luke Kenneth Casso... return read data out from Loadstore1 only when valid
2021-04-26 Luke Kenneth Casso... hook up MSR into MMU (TODO, use a lot less bits)
2021-04-23 Luke Kenneth Casso... move MMU Testcase to openpower.test
2021-04-23 Luke Kenneth Casso... import from openpower.endian
2021-04-23 Luke Kenneth Casso... use openpower.test.common
2021-04-23 Luke Kenneth Casso... more openpower-isa conversion
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-04-20 Luke Kenneth Casso... cannot pass in arguments to Core - must be done with...
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size
2021-03-02 Luke Kenneth Casso... comment out changing SPR 720 because 720 is not support...
2021-03-02 Luke Kenneth Casso... sort out SPR setting in MMU
2021-03-02 Luke Kenneth Casso... operating correctly, not directing MMU SPRs to SPR...
2021-03-02 Luke Kenneth Casso... must always set ok for writing out data otherwise it...
2021-02-24 Tobias Platenupdate mmu testcase
2021-02-20 Luke Kenneth Casso... correct arguments, set microwatt_mmu=True, pass in...
2021-02-20 Luke Kenneth Casso... minor whitespace cleanup
2021-02-20 Tobias Platenmmu testcase: set MMU SPRs
2021-02-20 Tobias Platenadd rom debugger
2021-02-20 Tobias Platenadd mmu rom testcase
2021-02-18 Tobias Platenmmu: remove TestMemory
2021-02-16 Tobias Platenmmureq handling
2021-02-16 Tobias Platendcache error handling
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-15 Tobias Platentest case for MMU SPRs: PID and PRTBL
2021-02-05 Tobias Platenfix hanging simulation
2021-02-04 Tobias Platensrc/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
2021-02-04 Tobias Platenupdate test_issuer_mmu_data_path.py to handle SPRs
2021-01-19 Tobias Platentest_issuer_mmu_data_path.py: test both ld and st instr...
2021-01-19 Tobias Platenconnect LDSTException to MMU and DCache
2021-01-19 Tobias Platenconnect wishbone bus to test memory
2021-01-18 Tobias Platenfu/mmu/fsm.py: connect valid and load signals
2021-01-17 Tobias Platenadd test memory for simulation
2021-01-17 Tobias Platencleanup test_issuer_mmu_data_path.py
2021-01-16 Tobias Platenclean up test case for tlbie and dcbz
2021-01-16 Tobias Platenmove microwatt_mmu bool variable to pspec
2021-01-16 Tobias Platenadd new unittest: test_issuer_mmu_data_path.py
2021-01-15 Tobias Platencleanup test_non_production_core.py
2021-01-15 Tobias Platentest_non_production_core.py: fix hanging test
2021-01-15 Tobias Platentest_non_production_core.py: wire instruction decoder...
2021-01-14 Tobias Platenadd test case for mmu+NonProductionCore
2021-01-07 Tobias Platenset initial_sprs, cleanup mfspr testprog
2021-01-07 Tobias Platenmfspr is RT, SPR
2021-01-06 Tobias Platenfirst testcase for mmu: case_mfspr_after_invalid_load
2021-01-06 Tobias Platenfu/mmu/fsm.py: mfspr!=mtspr
2020-11-17 Tobias Platentestcase for dcbz
2020-11-16 Tobias Platenadd class LoadStore1(PortInterfaceBase)
2020-11-11 Tobias Platendcbz and tlbie first test, still incomplete
2020-11-11 Tobias Platenfu/mmu/test/test_pipe_caller.py test case for mfspr
2020-11-08 Tobias Platenmmu fsm testcase: add check_fsm_outputs based on functi...
2020-11-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-11-08 Tobias Platenmmu/fsm: test case for mtspr
2020-11-07 Tobias Platenfixed a bug in src/soc/fu/mmu/fsm.py
2020-11-04 Tobias PlatenMMU: begin test case for 'dcbz'
2020-11-03 Tobias Platenfix broken unittest after installing power-instruction...
2020-10-20 Tobias Platens/alu/fsm/g
2020-10-20 Tobias Platentest case for FSMMMUStage
2020-10-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-10-08 Tobias Platenadd WIP test_pipe_caller.py for mmu
2020-10-08 Luke Kenneth Casso... add incoming PortInterface to be connected to LoadStore...
2020-09-21 Luke Kenneth Casso... add missing file
2020-09-15 Luke Kenneth Casso... instantiate MMU from AllFunctionUnits
2020-09-15 Luke Kenneth Casso... do not need FAST regs in MMU
2020-09-15 Luke Kenneth Casso... add edge-triggering to dcache/mmu "valid"
2020-09-15 Luke Kenneth Casso... add OP_MFSPR to mmu
2020-09-15 Luke Kenneth Casso... use convenience vars
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