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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
fu
/
mul
/
pipe_data.py
2022-07-05
Luke Kenneth Casso...
MulOutputData was only 64-bit output not 128-bit
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2022-02-27
Luke Kenneth Casso...
start on converting MUL and DIV pipelines to XLEN
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2022-02-27
Luke Kenneth Casso...
convert from public static functions/properties for...
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2021-05-04
Luke Kenneth Casso...
rename IntegerData to FUBaseData
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2020-07-18
Luke Kenneth Casso...
missing conversion of DIV to Div
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2020-07-09
Luke Kenneth Casso...
remove unneeded xer.ca in MulOutputData
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2020-07-09
Luke Kenneth Casso...
add new stages etc. to get multiply working without...
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-06
Luke Kenneth Casso...
use ComMULOpSubset in mul pipeline
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2020-07-06
Luke Kenneth Casso...
investigating mul pipeline
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2020-07-06
Luke Kenneth Casso...
first cut at mul test pipeline
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2020-07-06
Luke Kenneth Casso...
add first cut at fu mul pipeline
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2020-05-22
Luke Kenneth Casso...
add cookie-cut mul pipeline template
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