Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / mul / pipe_data.py
2022-07-05 Luke Kenneth Casso... MulOutputData was only 64-bit output not 128-bit
2022-02-27 Luke Kenneth Casso... start on converting MUL and DIV pipelines to XLEN
2022-02-27 Luke Kenneth Casso... convert from public static functions/properties for...
2021-05-04 Luke Kenneth Casso... rename IntegerData to FUBaseData
2020-07-18 Luke Kenneth Casso... missing conversion of DIV to Div
2020-07-09 Luke Kenneth Casso... remove unneeded xer.ca in MulOutputData
2020-07-09 Luke Kenneth Casso... add new stages etc. to get multiply working without...
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-06 Luke Kenneth Casso... use ComMULOpSubset in mul pipeline
2020-07-06 Luke Kenneth Casso... investigating mul pipeline
2020-07-06 Luke Kenneth Casso... first cut at mul test pipeline
2020-07-06 Luke Kenneth Casso... add first cut at fu mul pipeline
2020-05-22 Luke Kenneth Casso... add cookie-cut mul pipeline template