Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / mul / pre_stage.py
2022-02-27 Luke Kenneth Casso... start on converting MUL and DIV pipelines to XLEN
2021-10-10 Luke Kenneth Casso... replace PartitionedSignal with SimdSignal
2020-07-18 Luke Kenneth Casso... missing conversion of DIV to Div
2020-07-09 Luke Kenneth Casso... add new stages etc. to get multiply working without...
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-06 Luke Kenneth Casso... investigating mul pipeline
2020-07-06 Luke Kenneth Casso... first cut at mul test pipeline
2020-07-06 Luke Kenneth Casso... add first cut at fu mul pipeline