remove unneeded imports
[soc.git] / src / soc / fu / shift_rot / pipe_data.py
2020-06-06 Luke Kenneth Casso... remove unneeded imports
2020-06-06 Luke Kenneth Casso... noticed the regular pattern in all pipe_data.py (regspecs).
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... remove rdflags in pipe_data.py (redundant)
2020-06-02 Luke Kenneth Casso... rename regspecs to give a consistent naming scheme
2020-06-01 Luke Kenneth Casso... okaaay add a "rdflags" function which obtains the yes...
2020-06-01 Luke Kenneth Casso... add shift-rot input record and use it
2020-06-01 Luke Kenneth Casso... put RB in 2nd position (matching immediate) in ShiftRot...
2020-06-01 Luke Kenneth Casso... shiftrot uses LogicalOutputData not ALUOutputData
2020-05-22 Luke Kenneth Casso... remove sticky overflow from Shift Rot pipeline
2020-05-22 Luke Kenneth Casso... create common input pipe spec to avoid code-duplication
2020-05-21 Luke Kenneth Casso... move common functionality between PipeSpecs to soc...
2020-05-21 Luke Kenneth Casso... move FU IntegerData to directory below
2020-05-21 Luke Kenneth Casso... create and use ShiftRotPipeSpec
2020-05-20 Luke Kenneth Casso... add register specs to pipeline in/out so that they...
2020-05-20 Luke Kenneth Casso... fixup XER names in shift_rot pipe tests
2020-05-18 Luke Kenneth Casso... mass-rename of modules to soc.fu.*
2020-05-18 Luke Kenneth Casso... rename pipe to fu