sorting out bigendian/littleendian including in qemu
[soc.git] / src / soc / fu / shift_rot / test / test_pipe_caller.py
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-06-11 Luke Kenneth Casso... must distinguish between rd/write xer_ca sim helpers
2020-06-11 Luke Kenneth Casso... use ALUHelpers in shift_rot
2020-06-10 Luke Kenneth Casso... move to common ALUHelpers for ShiftRot test_pipe_caller.py
2020-06-07 Luke Kenneth Casso... add carry test to shift_rot test_pipe_caller: it fails...
2020-06-07 Luke Kenneth Casso... add extra args to ISA in test_pipe_caller.py
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... use common TestCase in shift_rot
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... convert shift_rot tests to use common get_cu_inputs...
2020-06-01 Luke Kenneth Casso... comment out rlwinm. for now
2020-06-01 Luke Kenneth Casso... add rlwinm. test instruction (sets CR0)
2020-05-24 Luke Kenneth Casso... start using Data in pipelines
2020-05-22 Luke Kenneth Casso... remove sticky overflow from Shift Rot pipeline
2020-05-22 Luke Kenneth Casso... create common input pipe spec to avoid code-duplication
2020-05-22 Luke Kenneth Casso... remove unneeded code
2020-05-21 Luke Kenneth Casso... move common functionality between PipeSpecs to soc...
2020-05-21 Luke Kenneth Casso... create and use ShiftRotPipeSpec
2020-05-20 Luke Kenneth Casso... fixup XER names in shift_rot pipe tests
2020-05-18 Luke Kenneth Casso... mass-rename of modules to soc.fu.*
2020-05-18 Luke Kenneth Casso... rename pipe to fu