move pc_i and svstate_i inside if self.run_hdl
[soc.git] / src / soc / fu / shift_rot /
2021-08-31 Luke Kenneth Casso... update ready/valid in shift_rot test_pipe_caller
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as...
2021-05-04 Luke Kenneth Casso... rename IntegerData to FUBaseData
2021-04-23 Luke Kenneth Casso... move LDST tests to openpower.test
2021-04-23 Luke Kenneth Casso... move shiftrot test cases to openpower.test
2021-04-23 Luke Kenneth Casso... import from openpower.endian
2021-04-23 Luke Kenneth Casso... use openpower.test.common
2021-04-23 Luke Kenneth Casso... more openpower-isa conversion
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-01-29 Luke Kenneth Casso... whoops missed out "+" on explicit license listing
2020-10-07 Luke Kenneth Casso... missing invert_in field from shiftrot input record
2020-10-06 Luke Kenneth Casso... use pdecode2.do not pdecode2.e in test_pipe_caller...
2020-09-27 Cesar StraussConvert yet another few tests to be able to use latest...
2020-09-07 Luke Kenneth Casso... convert shift_rot to subset decoder
2020-09-07 Luke Kenneth Casso... bit of a big reorg of data structures
2020-09-07 Luke Kenneth Casso... whoops truncated the mb and me fields
2020-09-05 Luke Kenneth Casso... add simple wishbone GPIO peripheral
2020-09-05 Samuel A. Falvo IIAdd unit test replicating failing proof case
2020-09-04 Luke Kenneth Casso... add sld test with RB=64 to see what happens
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... oink, write_cr shiftrot record width was zero (??)
2020-08-27 Luke Kenneth Casso... sorting out shift_rot to use new output stage data...
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-25 Luke Kenneth Casso... although shift-rot does not alter XER.so it still needs...
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-23 Luke Kenneth Casso... update copyright notices to include additional primary...
2020-08-23 Michael NolanAdd copyright to files in fu/ that I was the primary...
2020-08-22 Luke Kenneth Casso... bug in andc and orc, complement was taking place on...
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-19 Luke Kenneth Casso... rename and document fields in shift_rot proof
2020-08-19 Luke Kenneth Casso... use "Mask" class which is more gate-efficient than...
2020-08-14 Luke Kenneth Casso... divide shiftrot pipeline into 2 (simple last)
2020-08-03 Samuel A. Falvo IIWIP: check MB > ME and select mask appropriately
2020-08-01 Luke Kenneth Casso... add rlwnm test showing that shift rot OP_RLC proof...
2020-08-01 Luke Kenneth Casso... line-length / whitespace
2020-08-01 Luke Kenneth Casso... expand out for-loop setting up input record subset
2020-07-31 Samuel A. Falvo IIWIP: more debugging signals for inspection
2020-07-30 Samuel A. Falvo IIWIP: rlwinm/rlwnm/rlwimi-type proofs
2020-07-29 Luke Kenneth Casso... move SHIFTROT test out of subtest indentation
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-28 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-28 Luke Kenneth Casso... use ctx.op compare (and muxid) in shiftrot proof
2020-07-26 Luke Kenneth Casso... convert shift_rot test to new base accumulator style
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-21 Luke Kenneth Casso... make cxxsim optional and print warning
2020-07-16 Luke Kenneth Casso... more tidyup on use of CompOpSubsetBase
2020-07-14 Luke Kenneth Casso... set up masks for OP_RL* formal proof
2020-07-14 Luke Kenneth Casso... disable cxxsim test
2020-07-14 Luke Kenneth Casso... first attempt running cxxsim
2020-07-13 Luke Kenneth Casso... whitespace
2020-07-13 Luke Kenneth Casso... formal proof of OP_EXTSWSLI
2020-07-13 Luke Kenneth Casso... quick test showing how left/right mask work
2020-07-13 Luke Kenneth Casso... comments
2020-07-13 Luke Kenneth Casso... attempting formal proof of OP_EXTSWSLI
2020-07-13 Luke Kenneth Casso... reduce rotl module to one line (use bit_select)
2020-07-13 Luke Kenneth Casso... document rb as sh
2020-07-13 Luke Kenneth Casso... increase range of test values for extswsli
2020-07-13 Luke Kenneth Casso... add EXTSWSLI "pass" to formal shift_rot proof
2020-07-13 Luke Kenneth Casso... enable extswsli tests, fix spec-patching
2020-07-13 Luke Kenneth Casso... add regression test, simulator is wrong
2020-07-13 Luke Kenneth Casso... add simulator test against qemu for extswsli
2020-07-13 Luke Kenneth Casso... add extswsli unit test
2020-07-13 Luke Kenneth Casso... add link to rotator, sign-extend mode OP_EXTSWSLI
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-06-11 Luke Kenneth Casso... must distinguish between rd/write xer_ca sim helpers
2020-06-11 Luke Kenneth Casso... use ALUHelpers in shift_rot
2020-06-10 Luke Kenneth Casso... move to common ALUHelpers for ShiftRot test_pipe_caller.py
2020-06-07 Luke Kenneth Casso... wark-wark, do not & rs[0] into carry-out from rotator
2020-06-07 Luke Kenneth Casso... update rotator.py to match microwatt rotator.vhdl
2020-06-07 Luke Kenneth Casso... add carry test to shift_rot test_pipe_caller: it fails...
2020-06-07 Luke Kenneth Casso... add extra args to ISA in test_pipe_caller.py
2020-06-06 Luke Kenneth Casso... remove unneeded imports
2020-06-06 Luke Kenneth Casso... noticed the regular pattern in all pipe_data.py (regspecs).
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... use common TestCase in shift_rot
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... convert shift_rot tests to use common get_cu_inputs...
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... remove rdflags in pipe_data.py (redundant)
2020-06-02 Luke Kenneth Casso... rename regspecs to give a consistent naming scheme
2020-06-01 Luke Kenneth Casso... okaaay add a "rdflags" function which obtains the yes...
2020-06-01 Luke Kenneth Casso... more unneeded fields from SR InputRecord
2020-06-01 Luke Kenneth Casso... remove data_len from SR input record
2020-06-01 Luke Kenneth Casso... remove zero/invert from ShiftRot Input Record
2020-06-01 Luke Kenneth Casso... add shift-rot input record and use it
2020-06-01 Luke Kenneth Casso... rotator carry is set into both XER CA and CA32 fields
2020-06-01 Luke Kenneth Casso... comment out rlwinm. for now
2020-06-01 Luke Kenneth Casso... put RB in 2nd position (matching immediate) in ShiftRot...
2020-06-01 Luke Kenneth Casso... add rlwinm. test instruction (sets CR0)
2020-06-01 Luke Kenneth Casso... remove duplicate signal
2020-06-01 Luke Kenneth Casso... shiftrot uses LogicalOutputData not ALUOutputData
2020-05-27 Luke Kenneth Casso... check reg output Data.ok in shift_rot formal proof
2020-05-24 Luke Kenneth Casso... start using Data in pipelines
2020-05-22 Luke Kenneth Casso... add TODO and link to SHIFT_ROT formal bugreport
2020-05-22 Luke Kenneth Casso... remove xer.so from ShiftRot formal proof
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