Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / spr / main_stage.py
2022-04-30 Luke Kenneth Casso... clear out DEC in core.cur_state.dec due to spurious...
2022-01-20 Luke Kenneth Casso... whoops MFSPR DEC/TB was reading from FastRegs not StateRegs
2022-01-19 Luke Kenneth Casso... ISI (0x400) trap is the only one that puts memory-based...
2022-01-19 Luke Kenneth Casso... move DEC and TB into StateRegs, to make room in FastRegs
2021-12-09 Luke Kenneth Casso... include SPR.TB in SPR FU
2021-12-09 Jacob Lifshayformat code
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size
2020-09-06 Luke Kenneth Casso... minor code-munge on SPR-to-FAST mapping
2020-09-06 Luke Kenneth Casso... move DEC and TB from StateRegs to FastRegs for several...
2020-09-06 Luke Kenneth Casso... add DEC/TB SPRs to spr pipeline
2020-08-31 Luke Kenneth Casso... add XER to fastregs and "construct" it in mfspr/mtspr
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-04 Luke Kenneth Casso... debugging decoding of SPRs (fast)
2020-07-04 Luke Kenneth Casso... add spr test, add decode of spr in/out
2020-07-04 Luke Kenneth Casso... add spr main stage