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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
fu
/
spr
/ main_stage.py
2022-04-30
Luke Kenneth Casso...
clear out DEC in core.cur_state.dec due to spurious...
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2022-01-20
Luke Kenneth Casso...
whoops MFSPR DEC/TB was reading from FastRegs not StateRegs
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2022-01-19
Luke Kenneth Casso...
ISI (0x400) trap is the only one that puts memory-based...
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2022-01-19
Luke Kenneth Casso...
move DEC and TB into StateRegs, to make room in FastRegs
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2021-12-09
Luke Kenneth Casso...
include SPR.TB in SPR FU
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2021-12-09
Jacob Lifshay
format code
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2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
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2021-03-30
Alain D D Williams
Merge branch 'master' of git.libre-soc.org:soc
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2021-03-28
Luke Kenneth Casso...
rather invasive reduction of SPR regfile size
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2020-09-06
Luke Kenneth Casso...
minor code-munge on SPR-to-FAST mapping
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2020-09-06
Luke Kenneth Casso...
move DEC and TB from StateRegs to FastRegs for several...
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2020-09-06
Luke Kenneth Casso...
add DEC/TB SPRs to spr pipeline
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2020-08-31
Luke Kenneth Casso...
add XER to fastregs and "construct" it in mfspr/mtspr
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2020-07-12
Luke Kenneth Casso...
rename InternalOp to MicrOp
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-04
Luke Kenneth Casso...
debugging decoding of SPRs (fast)
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2020-07-04
Luke Kenneth Casso...
add spr test, add decode of spr in/out
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2020-07-04
Luke Kenneth Casso...
add spr main stage
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