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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
fu
/
spr
/ pipe_data.py
2022-04-30
Luke Kenneth Casso...
clear out DEC in core.cur_state.dec due to spurious...
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2022-02-27
Luke Kenneth Casso...
convert from public static functions/properties for...
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2022-01-19
Luke Kenneth Casso...
move DEC and TB into StateRegs, to make room in FastRegs
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2021-05-04
Luke Kenneth Casso...
rename IntegerData to FUBaseData
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2020-09-06
Luke Kenneth Casso...
move DEC and TB from StateRegs to FastRegs for several...
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2020-09-06
Luke Kenneth Casso...
add DEC/TB SPRs to spr pipeline
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2020-08-11
Luke Kenneth Casso...
reduce regfile ports by creating separate STATE regfile
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2020-07-14
Luke Kenneth Casso...
update docstrings
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-04
Luke Kenneth Casso...
add spr test, add decode of spr in/out
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2020-07-04
Luke Kenneth Casso...
add spr main stage
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2020-06-06
Luke Kenneth Casso...
remove unneeded imports
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2020-06-06
Luke Kenneth Casso...
noticed the regular pattern in all pipe_data.py (regspecs).
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2020-06-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-06-03
Luke Kenneth Casso...
convenience rename for spr pipe_data.py, consistent...
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2020-05-24
Luke Kenneth Casso...
add comments for SPR pipe_data
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2020-05-24
Luke Kenneth Casso...
add SPR pipe_data.py
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