Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / spr / pipe_data.py
2022-04-30 Luke Kenneth Casso... clear out DEC in core.cur_state.dec due to spurious...
2022-02-27 Luke Kenneth Casso... convert from public static functions/properties for...
2022-01-19 Luke Kenneth Casso... move DEC and TB into StateRegs, to make room in FastRegs
2021-05-04 Luke Kenneth Casso... rename IntegerData to FUBaseData
2020-09-06 Luke Kenneth Casso... move DEC and TB from StateRegs to FastRegs for several...
2020-09-06 Luke Kenneth Casso... add DEC/TB SPRs to spr pipeline
2020-08-11 Luke Kenneth Casso... reduce regfile ports by creating separate STATE regfile
2020-07-14 Luke Kenneth Casso... update docstrings
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-04 Luke Kenneth Casso... add spr test, add decode of spr in/out
2020-07-04 Luke Kenneth Casso... add spr main stage
2020-06-06 Luke Kenneth Casso... remove unneeded imports
2020-06-06 Luke Kenneth Casso... noticed the regular pattern in all pipe_data.py (regspecs).
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... convenience rename for spr pipe_data.py, consistent...
2020-05-24 Luke Kenneth Casso... add comments for SPR pipe_data
2020-05-24 Luke Kenneth Casso... add SPR pipe_data.py