Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / trap / main_stage.py
2022-07-04 Luke Kenneth Casso... add signal for resetting trap internal state (kaivb...
2022-07-04 Luke Kenneth Casso... set msr_o.data not msr_o Record in trap main_stage.py
2022-06-26 Luke Kenneth Casso... adapt TRAP function in main state pipeline to put KAIVB
2022-06-26 Luke Kenneth Casso... store KAIVB SPR 850 in TRAP Pipeline
2022-01-25 Luke Kenneth Casso... LDSTException now passing bits of SRR1 around to the...
2022-01-24 Luke Kenneth Casso... bool test on traptype to
2022-01-19 Luke Kenneth Casso... ISI (0x400) trap is the only one that puts memory-based...
2022-01-18 Luke Kenneth Casso... comments on SRR1 in trap
2022-01-18 Luke Kenneth Casso... preserve bits of SRR1 on a TRAP (including all interrup...
2022-01-17 Luke Kenneth Casso... fix hrfid and mtmsrd so that it is identical to microwatt
2021-12-22 Luke Kenneth Casso... use correct X-Form L field in OP_MTMSRD
2021-12-22 Luke Kenneth Casso... check problem state in OP_MTMSRD from original reg...
2021-05-04 Luke Kenneth Casso... add SVSTATE (SVSRR0) to TRAP pipeline
2021-05-04 Luke Kenneth Casso... adding fast3 SPR to Trap pipeline and unit test
2021-04-23 Luke Kenneth Casso... more openpower-isa conversion
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2020-10-06 Luke Kenneth Casso... add SRR1 setting for LDST memory exception trap
2020-09-06 Luke Kenneth Casso... comment, nothing unusual when Trap Type is DEC
2020-09-04 Luke Kenneth Casso... adding option to include XICS external interrupts.
2020-08-14 Luke Kenneth Casso... hack to get hrfid not to alter msr 51
2020-07-27 Luke Kenneth Casso... fix trap proof, and trap main_stage, and pseudocode...
2020-07-25 Luke Kenneth Casso... update comment-headers (TODO include page numbers to...
2020-07-24 Samuel A. Falvo IIWIP: addressing code review, restoring proofs, etc.
2020-07-24 Luke Kenneth Casso... got fed up with bit-slice ordering crap. cut it out
2020-07-24 Luke Kenneth Casso... code review comments for trap and proof
2020-07-24 Samuel A. Falvo IIRefactorin of common code
2020-07-24 Samuel A. Falvo IIAddress code review comments
2020-07-22 Luke Kenneth Casso... field number ordering wrong way round?
2020-07-22 Luke Kenneth Casso... review trap main_stage.py modifications: we are not...
2020-07-21 Samuel A. Falvo IICompleted SC FV properties
2020-07-21 Samuel A. Falvo IIRefine properties to comply with spec
2020-07-21 Luke Kenneth Casso... move cia and msr to trap input record
2020-07-21 Luke Kenneth Casso... add msr exception bits setting function in hardware
2020-07-21 Luke Kenneth Casso... correct trap spec page interrupt ref
2020-07-18 Luke Kenneth Casso... whoops use slice not range
2020-07-18 Luke Kenneth Casso... syntax error
2020-07-18 Luke Kenneth Casso... review of OP_RFID showed up some errors
2020-07-18 Luke Kenneth Casso... corrections to trap main_stage.py OP_RFID according...
2020-07-15 Luke Kenneth Casso... remove unneeded comment in trap msin stage
2020-07-15 Luke Kenneth Casso... move traptype to soc.consts
2020-07-13 Luke Kenneth Casso... add mtmsrd instruction and unit test
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-06 Luke Kenneth Casso... adding OP_MTMSR test
2020-07-05 Luke Kenneth Casso... add mtmsr tests (fail)
2020-07-05 Luke Kenneth Casso... check msr in trap test, fix OP_RFID
2020-07-04 Luke Kenneth Casso... cater for illegal instruction (generates a trap)
2020-07-04 Luke Kenneth Casso... add sc back in
2020-07-04 Luke Kenneth Casso... comments in trap about exceptions using microcoding
2020-07-04 Luke Kenneth Casso... update trap docstring
2020-07-04 Luke Kenneth Casso... use new consts module
2020-07-01 Luke Kenneth Casso... continue debugging trap pipeline
2020-07-01 Luke Kenneth Casso... debugging trap pipeline
2020-07-01 Luke Kenneth Casso... start running trap unit test, fixing errors
2020-06-09 Luke Kenneth Casso... correct local variable references
2020-06-09 Luke Kenneth Casso... bit more on TRAP handling (preparing priv instruction)
2020-06-08 Luke Kenneth Casso... add traptype and trapaddr to PowerDecoder2. idea is...
2020-06-08 Luke Kenneth Casso... found section in 3.0B PDF that refers to "Program Inter...
2020-06-08 Luke Kenneth Casso... copy MSR into SRR1 in trap function
2020-06-08 colepoirierFix spelling
2020-06-07 Luke Kenneth Casso... update trap with comments
2020-06-07 colepoirierAdd TrapMainStage.trap() convenience function to set...
2020-06-07 Luke Kenneth Casso... move MSR_PR checking to separate functiong
2020-06-07 colepoirierFix missing 'comb +='
2020-06-05 Luke Kenneth Casso... update comments
2020-06-05 Luke Kenneth Casso... more comments
2020-06-05 Luke Kenneth Casso... more comments
2020-06-05 Luke Kenneth Casso... a_i not b_in
2020-06-05 Luke Kenneth Casso... add comments
2020-06-05 colepoirierMade small changes to fu/trap/main_stage to bring nmige...
2020-06-05 Luke Kenneth Casso... refer to srr0/1 not a/b
2020-06-05 Luke Kenneth Casso... add msr_copy function and use it in OP_TRAP, OP_RFID...
2020-06-05 Luke Kenneth Casso... set SRR0 in OP_SC
2020-06-04 colepoirierUse a_i and b_i convenience variables instead of a...
2020-06-04 Luke Kenneth Casso... mention convenience variables
2020-06-04 Luke Kenneth Casso... rename trap to use convenience variables
2020-06-04 colepoirierUndo damage done by deleting VHDL microwatt comments,
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 colepoirierFixed missing nia.ok.eq(1) in OP_RFID
2020-06-03 colepoirierFixed merge conflict by using remote changes
2020-06-03 Luke Kenneth Casso... convenience variables
2020-06-03 Luke Kenneth Casso... FormX not FormXL
2020-06-03 Luke Kenneth Casso... add bit more TODO
2020-06-03 Luke Kenneth Casso... add more TODOs
2020-06-03 colepoirierFixed OP_RFID and OP_SC in fu/trap/main_stage
2020-06-03 Luke Kenneth Casso... add some more constants and ref to POWER9 pdf
2020-06-03 Luke Kenneth Casso... add an if for OP_MTMSR and some comments
2020-06-03 colepoirierAttempted to fix OP_RFID in TRAP pipeline
2020-06-02 colepoirierImplement TRAP instructions OP_RFID and OP_SC
2020-06-02 Luke Kenneth Casso... add MSR constants, TODO translated
2020-06-02 Luke Kenneth Casso... add TODO comments from microwatt source code
2020-05-27 Luke Kenneth Casso... code-morph, add TODO on OP_RFID, OP_SC, OP_ADDPCIS
2020-05-24 Luke Kenneth Casso... copy code for MTMSR from microwatt into comments
2020-05-24 Luke Kenneth Casso... add links for trap main stage
2020-05-24 Luke Kenneth Casso... add untested OP_MTMSR and OP_MFMSR
2020-05-24 Luke Kenneth Casso... TODO mention OP_MTMSR/OP_MFMSR
2020-05-21 Luke Kenneth Casso... add dedicated TrapPipeSpec
2020-05-19 Luke Kenneth Casso... rename module, remove extraneous code and imports
2020-05-19 Luke Kenneth Casso... hmmm, branch sets nia to Data as well and sets nia...
2020-05-19 Luke Kenneth Casso... use Data on SPRs in Trap InputData just like in BranchO...
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