test_compldst_multi_mmu.py: use nmigen.back.pysim
[soc.git] / src / soc / fu / trap / trap_input_record.py
2021-07-14 Luke Kenneth Casso... update SVSTATE to 64 bit length (fortunately very easy)
2021-05-04 Luke Kenneth Casso... add SVSTATE (SVSRR0) to TRAP pipeline
2021-04-26 Luke Kenneth Casso... hook up MSR into MMU (TODO, use a lot less bits)
2021-04-23 Luke Kenneth Casso... more openpower-isa conversion
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2020-10-06 Luke Kenneth Casso... passing LDSTException over to Trap Pipeline
2020-10-06 Luke Kenneth Casso... add LDSTException decode/handling in PowerDecoder2
2020-07-22 Luke Kenneth Casso... add TT.size and use it in PowerDecoder and trap input...
2020-07-21 Luke Kenneth Casso... move cia and msr to trap input record
2020-07-15 Luke Kenneth Casso... use new CompOpSubsetBase in trap
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-04 Luke Kenneth Casso... cater for illegal instruction (generates a trap)
2020-07-01 Luke Kenneth Casso... start running trap unit test, fixing errors